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feat[libcpu][cortex-m4]: Add interrupt state query helpers for Cortex-M4
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libcpu/arm/cortex-m4/cpuport.c

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@@ -436,6 +436,79 @@ void rt_hw_cpu_reset(void)
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SCB_AIRCR = SCB_RESET_VALUE;
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}
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/**
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\brief Get IPSR Register
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\details Returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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rt_inline rt_uint32_t __get_IPSR(void)
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{
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#if defined(__CC_ARM)
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register uint32_t __regIPSR __asm("ipsr");
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return(__regIPSR);
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#elif defined(__clang__)
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uint32_t result;
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__asm volatile ("MRS %0, ipsr" : "=r" (result) );
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return(result);
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#elif defined(__IAR_SYSTEMS_ICC__)
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return __iar_builtin_rsr("IPSR");
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#elif defined ( __GNUC__ )
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uint32_t result;
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__asm volatile ("MRS %0, ipsr" : "=r" (result) );
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return(result);
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#endif
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}
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/**
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* @brief This function will return the nest of interrupt.
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*
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* User application can invoke this function to get whether current
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* context is interrupt context.
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*
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* @return the number of nested interrupts.
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*/
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rt_uint8_t rt_interrupt_get_nest(void)
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{
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return (__get_IPSR() != 0);
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}
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/**
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\brief Get PRIMASK Register
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\details Returns the content of the PRIMASK Register.
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\return PRIMASK Register value
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*/
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rt_inline rt_uint32_t rt_hw_get_primask_value(void)
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{
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#if defined(__CC_ARM)
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register uint32_t __regPRIMASK __asm("primask");
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return (__regPRIMASK);
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#elif defined(__clang__)
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uint32_t result;
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__asm volatile ("MRS %0, primask" : "=r" (result));
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return result;
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#elif defined(__IAR_SYSTEMS_ICC__)
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return __iar_builtin_rsr("PRIMASK");
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#elif defined(__GNUC__)
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uint32_t result;
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__asm volatile ("MRS %0, primask" : "=r" (result));
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return result;
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#endif
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}
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/**
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* @brief Check whether maskable interrupts are currently disabled.
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*
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* @details
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* For Cortex-M4, interrupts are considered disabled when either:
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* - PRIMASK masks all configurable interrupts.
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*
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* @return RT_TRUE if interrupts are masked; otherwise RT_FALSE.
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*/
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rt_bool_t rt_hw_interrupt_is_disabled(void)
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{
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return ((rt_hw_get_primask_value() & 0x1UL) != 0UL);
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}
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#ifdef RT_USING_CPU_FFS
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/**
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* This function finds the first bit set (beginning with the least significant bit)

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