@@ -436,6 +436,79 @@ void rt_hw_cpu_reset(void)
436436 SCB_AIRCR = SCB_RESET_VALUE ;
437437}
438438
439+ /**
440+ \brief Get IPSR Register
441+ \details Returns the content of the IPSR Register.
442+ \return IPSR Register value
443+ */
444+ rt_inline rt_uint32_t __get_IPSR (void )
445+ {
446+ #if defined(__CC_ARM )
447+ register uint32_t __regIPSR __asm("ipsr" );
448+ return (__regIPSR );
449+ #elif defined(__clang__ )
450+ uint32_t result ;
451+ __asm volatile ("MRS %0, ipsr" : "=r" (result ) );
452+ return (result );
453+ #elif defined(__IAR_SYSTEMS_ICC__ )
454+ return __iar_builtin_rsr ("IPSR" );
455+ #elif defined ( __GNUC__ )
456+ uint32_t result ;
457+ __asm volatile ("MRS %0, ipsr" : "=r" (result ) );
458+ return (result );
459+ #endif
460+ }
461+
462+ /**
463+ * @brief This function will return the nest of interrupt.
464+ *
465+ * User application can invoke this function to get whether current
466+ * context is interrupt context.
467+ *
468+ * @return the number of nested interrupts.
469+ */
470+ rt_uint8_t rt_interrupt_get_nest (void )
471+ {
472+ return (__get_IPSR () != 0 );
473+ }
474+
475+ /**
476+ \brief Get PRIMASK Register
477+ \details Returns the content of the PRIMASK Register.
478+ \return PRIMASK Register value
479+ */
480+ rt_inline rt_uint32_t rt_hw_get_primask_value (void )
481+ {
482+ #if defined(__CC_ARM )
483+ register uint32_t __regPRIMASK __asm("primask" );
484+ return (__regPRIMASK );
485+ #elif defined(__clang__ )
486+ uint32_t result ;
487+ __asm volatile ("MRS %0, primask" : "=r" (result ));
488+ return result ;
489+ #elif defined(__IAR_SYSTEMS_ICC__ )
490+ return __iar_builtin_rsr ("PRIMASK" );
491+ #elif defined(__GNUC__ )
492+ uint32_t result ;
493+ __asm volatile ("MRS %0, primask" : "=r" (result ));
494+ return result ;
495+ #endif
496+ }
497+
498+ /**
499+ * @brief Check whether maskable interrupts are currently disabled.
500+ *
501+ * @details
502+ * For Cortex-M4, interrupts are considered disabled when either:
503+ * - PRIMASK masks all configurable interrupts.
504+ *
505+ * @return RT_TRUE if interrupts are masked; otherwise RT_FALSE.
506+ */
507+ rt_bool_t rt_hw_interrupt_is_disabled (void )
508+ {
509+ return ((rt_hw_get_primask_value () & 0x1UL ) != 0UL );
510+ }
511+
439512#ifdef RT_USING_CPU_FFS
440513/**
441514 * This function finds the first bit set (beginning with the least significant bit)
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