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[bsp/rockchip]Add CI compilation checks for RK3500 BSP.
1 parent c632885 commit 7071ba3

12 files changed

Lines changed: 216 additions & 24 deletions

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‎.github/ALL_BSP_COMPILE.json‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -398,6 +398,14 @@
398398
"zynqmp-a53-dfzu2eg"
399399
]
400400
},
401+
{
402+
"RTT_BSP": "aarch64-bsp-smart",
403+
"RTT_TOOL_CHAIN": "sourcery-aarch64",
404+
"RTT_SMART_TOOL_CHAIN": "aarch64-linux-musleabi",
405+
"SUB_RTT_BSP": [
406+
"rockchip/rk3500"
407+
]
408+
},
401409
{
402410
"RTT_BSP": "riscv-none",
403411
"RTT_TOOL_CHAIN": "sourcery-riscv-none-embed",

‎.github/workflows/bsp_buildings.yml‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ jobs:
144144
echo "RTT_EXEC_PATH=/opt/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64/bin" >> $GITHUB_ENV
145145
146146
- name: Install AArch64 ToolChains
147-
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && success() }}
147+
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN != 'aarch64-linux-musleabi' && success() }}
148148
shell: bash
149149
run: |
150150
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.6/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz
@@ -153,6 +153,17 @@ jobs:
153153
echo "RTT_EXEC_PATH=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf/bin" >> $GITHUB_ENV
154154
sudo apt-get -qq install device-tree-compiler
155155
156+
- name: Install AArch64 RT-Smart ToolChains
157+
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-aarch64' && matrix.legs.RTT_SMART_TOOL_CHAIN == 'aarch64-linux-musleabi' && success() }}
158+
shell: bash
159+
run: |
160+
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.7/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2
161+
sudo tar xjf aarch64-linux-musleabi_for_x86_64-pc-linux-gnu_stable.tar.bz2 -C /opt
162+
/opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin/aarch64-linux-musleabi-gcc --version
163+
echo "RTT_EXEC_PATH=/opt/aarch64-linux-musleabi_for_x86_64-pc-linux-gnu/bin" >> $GITHUB_ENV
164+
echo "RTT_CC_PREFIX=aarch64-linux-musleabi-" >> $GITHUB_ENV
165+
sudo apt-get -qq install device-tree-compiler
166+
156167
- name: Install Mips ToolChains
157168
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
158169
shell: bash

‎bsp/rockchip/dm/clk/clk-rk-pll.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1440,6 +1440,11 @@ void rockchip_pll_clk_cell_init(struct rockchip_clk_cell *rk_cell)
14401440
{
14411441
struct rockchip_pll_clk_cell *pll_clk_cell = cell_to_rockchip_pll_clk_cell(&rk_cell->cell);
14421442

1443+
if (rk_cell->cell.parents_nr == 1 && rk_cell->cell.parent_names)
1444+
{
1445+
rk_cell->cell.parent_name = rk_cell->cell.parent_names[0];
1446+
}
1447+
14431448
rk_cell->muxdiv_offset = pll_clk_cell->mode_offset;
14441449
rk_cell->mux_shift = pll_clk_cell->mode_shift;
14451450

‎bsp/rockchip/dm/clk/clk-rk-pll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ struct rockchip_pll_clk_cell
112112
#define PLL_RAW(_type, _id, _name, _pnames, _pnames_nr, _flags, _con, _mode, _mshift, _lshift, _glock, _pflags, _rtable) \
113113
{ \
114114
.rk_cell.cell.name = _name, \
115-
.rk_cell.cell.parent_names = (void *)_pnames, \
115+
.rk_cell.cell.parent_names = _pnames, \
116116
.rk_cell.cell.parents_nr = _pnames_nr, \
117117
.rk_cell.cell.flags = RT_CLK_F_GET_RATE_NOCACHE | _flags, \
118118
.rk_cell.id = _id, \

‎bsp/rockchip/dm/clk/clk-rk3308.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ static const struct rockchip_cpu_clk_reg_data rk3308_cpu_clk_data =
154154
.mux_core_mask = 0x3,
155155
};
156156

157-
PNAME(mux_pll_p) = "xin24m";
157+
PNAMES(mux_pll_p) = { "xin24m" };
158158
PNAMES(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
159159
PNAMES(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
160160
PNAMES(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
@@ -216,16 +216,16 @@ static rt_uint32_t uart_src_mux_idx[] = { 3, 4, 0, 1, 2 };
216216
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
217217

218218
static struct rockchip_pll_clk_cell rk3308_pll_apll =
219-
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, 0, RK3308_PLL_CON(0), RK3308_MODE_CON,
219+
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(0), RK3308_MODE_CON,
220220
0, 0, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates);
221221
static struct rockchip_pll_clk_cell rk3308_pll_dpll =
222-
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, 0, RK3308_PLL_CON(8), RK3308_MODE_CON,
222+
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(8), RK3308_MODE_CON,
223223
2, 1, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates);
224224
static struct rockchip_pll_clk_cell rk3308_pll_vpll0 =
225-
PLL_RAW(pll_type_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, 1, 0, RK3308_PLL_CON(16), RK3308_MODE_CON,
225+
PLL_RAW(pll_type_rk3328, PLL_VPLL0, "vpll0", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(16), RK3308_MODE_CON,
226226
4, 2, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates);
227227
static struct rockchip_pll_clk_cell rk3308_pll_vpll1 =
228-
PLL_RAW(pll_type_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, 1, 0, RK3308_PLL_CON(24), RK3308_MODE_CON,
228+
PLL_RAW(pll_type_rk3328, PLL_VPLL1, "vpll1", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3308_PLL_CON(24), RK3308_MODE_CON,
229229
6, 3, RK3308_GRF_SOC_STATUS0, 0, rk3308_pll_rates);
230230

231231
static struct rockchip_clk_cell rk3308_uart0_fracmux =

‎bsp/rockchip/dm/clk/clk-rk3528.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ static const struct rockchip_cpu_clk_reg_data rk3528_cpu_clk_data =
160160
.mux_core_mask = 0x1,
161161
};
162162

163-
PNAME(mux_pll_p) = "xin24m";
163+
PNAMES(mux_pll_p) = { "xin24m" };
164164
PNAMES(mux_24m_32k_p) = { "xin24m", "clk_32k" };
165165
PNAMES(mux_gpll_cpll_p) = { "gpll", "cpll" };
166166
PNAMES(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
@@ -200,19 +200,19 @@ PNAMES(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" };
200200
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
201201

202202
static struct rockchip_pll_clk_cell rk3528_pll_apll =
203-
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON,
203+
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(0), RK3528_MODE_CON,
204204
0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates);
205205
static struct rockchip_pll_clk_cell rk3528_pll_cpll =
206-
PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON,
206+
PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(8), RK3528_MODE_CON,
207207
2, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates);
208208
static struct rockchip_pll_clk_cell rk3528_pll_gpll =
209-
PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON,
209+
PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PLL_CON(24), RK3528_MODE_CON,
210210
4, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates);
211211
static struct rockchip_pll_clk_cell rk3528_pll_ppll =
212-
PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON,
212+
PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), RK3528_MODE_CON,
213213
6, 0, RK3528_GRF_SOC_STATUS0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates);
214214
static struct rockchip_pll_clk_cell rk3528_pll_dpll =
215-
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON,
215+
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), RK3528_DDRPHY_MODE_CON,
216216
0, 0, RK3528_GRF_SOC_STATUS0, 0, rk3528_pll_rates);
217217

218218
static struct rockchip_clk_cell rk3528_uart0_fracmux =

‎bsp/rockchip/dm/clk/clk-rk3568.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@ static const struct rockchip_cpu_clk_reg_data rk3568_cpu_clk_data =
264264
.mux_core_mask = 0x1,
265265
};
266266

267-
PNAME(mux_pll_p) = "xin24m";
267+
PNAMES(mux_pll_p) = { "xin24m" };
268268
PNAMES(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
269269
PNAMES(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" };
270270
PNAMES(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" };
@@ -375,29 +375,29 @@ PNAMES(i2s3_mclk_ioe_p) = { "i2s3_mclkin", "i2s3_mclkout" };
375375
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
376376

377377
static struct rockchip_pll_clk_cell rk3568_pmu_pll_ppll =
378-
PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, 1, 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0,
378+
PLL_RAW(pll_type_rk3328, PLL_PPLL, "ppll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PMU_PLL_CON(0), RK3568_PMU_MODE_CON0,
379379
0, 4, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
380380
static struct rockchip_pll_clk_cell rk3568_pmu_pll_hpll =
381-
PLL_RAW(pll_type_rk3328, PLL_HPLL, "hpll", mux_pll_p, 1, 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0,
381+
PLL_RAW(pll_type_rk3328, PLL_HPLL, "hpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PMU_PLL_CON(16), RK3568_PMU_MODE_CON0,
382382
2, 7, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
383383

384384
static struct rockchip_pll_clk_cell rk3568_pll_apll =
385-
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, 1, 0, RK3568_PLL_CON(0), RK3568_MODE_CON0,
385+
PLL_RAW(pll_type_rk3328, PLL_APLL, "apll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(0), RK3568_MODE_CON0,
386386
0, 0, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
387387
static struct rockchip_pll_clk_cell rk3568_pll_dpll =
388-
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, 1, 0, RK3568_PLL_CON(8), RK3568_MODE_CON0,
388+
PLL_RAW(pll_type_rk3328, PLL_DPLL, "dpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(8), RK3568_MODE_CON0,
389389
2, 1, RK3568_GRF_SOC_STATUS0, 0, RT_NULL);
390390
static struct rockchip_pll_clk_cell rk3568_pll_cpll =
391-
PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, 1, 0, RK3568_PLL_CON(24), RK3568_MODE_CON0,
391+
PLL_RAW(pll_type_rk3328, PLL_CPLL, "cpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(24), RK3568_MODE_CON0,
392392
4, 2, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
393393
static struct rockchip_pll_clk_cell rk3568_pll_gpll =
394-
PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, 1, 0, RK3568_PLL_CON(16), RK3568_MODE_CON0,
394+
PLL_RAW(pll_type_rk3328, PLL_GPLL, "gpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(16), RK3568_MODE_CON0,
395395
6, 3, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
396396
static struct rockchip_pll_clk_cell rk3568_pll_npll =
397-
PLL_RAW(pll_type_rk3328, PLL_NPLL, "npll", mux_pll_p, 1, RT_CLK_F_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0,
397+
PLL_RAW(pll_type_rk3328, PLL_NPLL, "npll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), RT_CLK_F_IS_CRITICAL, RK3568_PLL_CON(32), RK3568_MODE_CON0,
398398
10, 5, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
399399
static struct rockchip_pll_clk_cell rk3568_pll_vpll =
400-
PLL_RAW(pll_type_rk3328, PLL_VPLL, "vpll", mux_pll_p, 1, 0, RK3568_PLL_CON(40), RK3568_MODE_CON0,
400+
PLL_RAW(pll_type_rk3328, PLL_VPLL, "vpll", mux_pll_p, RT_ARRAY_SIZE(mux_pll_p), 0, RK3568_PLL_CON(40), RK3568_MODE_CON0,
401401
12, 6, RK3568_GRF_SOC_STATUS0, 0, rk3568_pll_rates);
402402

403403
static struct rockchip_clk_cell rk3568_i2s0_8ch_tx_fracmux =

‎bsp/rockchip/rk3300/rtconfig.py‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
import os
2+
import subprocess
23

34
# toolchains options
45
ARCH ='aarch64'
@@ -34,11 +35,22 @@
3435
OBJDUMP = PREFIX + 'objdump'
3536
OBJCPY = PREFIX + 'objcopy'
3637

38+
def _ld_option_supported(ld_path, option):
39+
try:
40+
return subprocess.call([ld_path, option],
41+
stdout=subprocess.DEVNULL,
42+
stderr=subprocess.DEVNULL) == 0
43+
except OSError:
44+
return False
45+
46+
_ld_path = os.path.join(EXEC_PATH, PREFIX + 'ld')
47+
_ldflags_rwx = ' -Wl,--no-warn-rwx-segments' if _ld_option_supported(_ld_path, '--no-warn-rwx-segments') else ''
48+
3749
DEVICE = ' -g -march=armv8-a -mtune=cortex-a35 -fdiagnostics-color=always'
3850
CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp'
3951
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
4052
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
41-
LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-warn-rwx-segments -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
53+
LFLAGS = DEVICE + ' -nostartfiles' + _ldflags_rwx + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
4254
CPATH = ''
4355
LPATH = ''
4456

@@ -52,3 +64,9 @@
5264

5365
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
5466
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
67+
68+
def dist_handle(BSP_ROOT, dist_dir):
69+
import sys
70+
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
71+
from sdk_dist import dist_do_building
72+
dist_do_building(BSP_ROOT, dist_dir)

‎bsp/rockchip/rk3500/.ci/attachconfig/ci.attachconfig.yml‎

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,81 @@
1+
scons.args: &scons
2+
scons_arg:
3+
- '--strict'
4+
5+
devices.dm.all:
6+
<<: *scons
7+
kconfig:
8+
- CONFIG_RT_USING_DM=y
9+
- CONFIG_RT_USING_OFW=y
10+
- CONFIG_RT_USING_RESET=y
11+
- CONFIG_RT_USING_PIN=y
12+
- CONFIG_RT_USING_PINCTRL=y
13+
- CONFIG_RT_USING_CLK=y
14+
- CONFIG_RT_USING_REGULATOR=y
15+
- CONFIG_RT_USING_PIC=y
16+
- CONFIG_RT_USING_MFD=y
17+
- CONFIG_RT_MFD_SYSCON=y
18+
- CONFIG_RT_MFD_RK8XX=y
19+
- CONFIG_RT_USING_ADC=y
20+
- CONFIG_RT_ADC_ROCKCHIP_SARADC=y
21+
- CONFIG_RT_USING_CAN=y
22+
- CONFIG_RT_CAN_USING_CANFD=y
23+
- CONFIG_RT_CAN_CANFD_ROCKCHIP=y
24+
- CONFIG_RT_USING_CLOCK_TIME=y
25+
- CONFIG_RT_CLOCK_TIMER_ROCKCHIP=y
26+
- CONFIG_RT_USING_I2C=y
27+
- CONFIG_RT_I2C_RK3X=y
28+
- CONFIG_RT_USING_PWM=y
29+
- CONFIG_RT_PWM_ROCKCHIP=y
30+
- CONFIG_RT_USING_RTC=y
31+
- CONFIG_RT_RTC_RK8XX=y
32+
- CONFIG_RT_RTC_RK_TIMER=y
33+
- CONFIG_RT_USING_SDIO=y
34+
- CONFIG_RT_SDIO_DW_MMC=y
35+
- CONFIG_RT_SDIO_DW_MMC_ROCKCHIP=y
36+
- CONFIG_RT_USING_SPI=y
37+
- CONFIG_RT_USING_QSPI=y
38+
- CONFIG_RT_USING_DMA=y
39+
- CONFIG_RT_SPI_ROCKCHIP=y
40+
- CONFIG_RT_SPI_ROCKCHIP_SFC=y
41+
- CONFIG_RT_USING_WDT=y
42+
- CONFIG_RT_WDT_RK8XX=y
43+
- CONFIG_RT_USING_HWCRYPTO=y
44+
- CONFIG_RT_HWCRYPTO_USING_RNG=y
45+
- CONFIG_RT_HWCRYPTO_RNG_ROCKCHIP=y
46+
- CONFIG_RT_USING_INPUT=y
47+
- CONFIG_RT_INPUT_MISC=y
48+
- CONFIG_RT_INPUT_MISC_PWRKEY_RK8XX=y
49+
- CONFIG_RT_USING_MBOX=y
50+
- CONFIG_RT_MBOX_ROCKCHIP=y
51+
- CONFIG_RT_USING_HWSPINLOCK=y
52+
- CONFIG_RT_HWSPINLOCK_ROCKCHIP=y
53+
- CONFIG_RT_USING_PHYE=y
54+
- CONFIG_RT_PHYE_ROCKCHIP_NANENG_COMBO=y
55+
- CONFIG_RT_PHYE_ROCKCHIP_SNPS_PCIE3=y
56+
- CONFIG_RT_MFD_RK8XX_I2C=y
57+
- CONFIG_RT_MFD_RK8XX_SPI=y
58+
- CONFIG_RT_REGULATOR_RK8XX=y
59+
- CONFIG_RT_PMDOMAIN_ROCKCHIP=y
60+
- CONFIG_RT_USING_THERMAL=y
61+
- CONFIG_RT_THERMAL_ROCKCHIP_TSADC=y
62+
- CONFIG_RT_USING_NVMEM=y
63+
- CONFIG_RT_NVMEM_ROCKCHIP_OTP=y
64+
- CONFIG_RT_USING_PCI=y
65+
- CONFIG_RT_PCI_DW=y
66+
- CONFIG_RT_PCI_DW_ROCKCHIP=y
67+
- CONFIG_RT_PIN_ROCKCHIP=y
68+
- CONFIG_RT_PINCTRL_ROCKCHIP_RK8XX=y
69+
- CONFIG_RT_PINCTRL_ROCKCHIP=y
70+
- CONFIG_RT_CLK_ROCKCHIP_RK8XX_CLKOUT=y
71+
- CONFIG_RT_CLK_ROCKCHIP_LINK=y
72+
- CONFIG_RT_CLK_ROCKCHIP=y
73+
- CONFIG_RT_CLK_ROCKCHIP_RK3308=y
74+
- CONFIG_RT_CLK_ROCKCHIP_RK3528=y
75+
- CONFIG_RT_CLK_ROCKCHIP_RK3568=y
76+
- CONFIG_RT_CLK_ROCKCHIP_RK3576=y
77+
- CONFIG_RT_CLK_ROCKCHIP_RK3588=y
78+
- CONFIG_RT_SOC_ROCKCHIP_FIQ_DEBUGGER=y
79+
- CONFIG_RT_SOC_ROCKCHIP_GRF=y
80+
- CONFIG_RT_SOC_ROCKCHIP_HW_DECOMPRESS=y
81+
- CONFIG_RT_SOC_ROCKCHIP_IODOMAIN=y

‎bsp/rockchip/rk3500/rtconfig.py‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
import os
2+
import subprocess
23

34
# toolchains options
45
ARCH ='aarch64'
@@ -34,14 +35,25 @@
3435
OBJDUMP = PREFIX + 'objdump'
3536
OBJCPY = PREFIX + 'objcopy'
3637

38+
def _ld_option_supported(ld_path, option):
39+
try:
40+
return subprocess.call([ld_path, option],
41+
stdout=subprocess.DEVNULL,
42+
stderr=subprocess.DEVNULL) == 0
43+
except OSError:
44+
return False
45+
46+
_ld_path = os.path.join(EXEC_PATH, PREFIX + 'ld')
47+
_ldflags_rwx = ' -Wl,--no-warn-rwx-segments' if _ld_option_supported(_ld_path, '--no-warn-rwx-segments') else ''
48+
3749
# For Cortex-A55/A76
3850
# DEVICE = ' -g -march=armv8.2-a -mtune=cortex-a55 -fdiagnostics-color=always'
3951
# For Cortex-A53/A72
4052
DEVICE = ' -g -mcpu=cortex-a53 -fdiagnostics-color=always'
4153
CPPFLAGS= ' -nostdinc -undef -E -P -x assembler-with-cpp'
4254
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
4355
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
44-
LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-warn-rwx-segments -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
56+
LFLAGS = DEVICE + ' -nostartfiles' + _ldflags_rwx + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
4557
CPATH = ''
4658
LPATH = ''
4759

@@ -58,3 +70,9 @@
5870
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
5971
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
6072
POST_ACTION += 'md5sum rtthread.bin\n'
73+
74+
def dist_handle(BSP_ROOT, dist_dir):
75+
import sys
76+
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
77+
from sdk_dist import dist_do_building
78+
dist_do_building(BSP_ROOT, dist_dir)

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