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[BSP] ADD ns800 BSP
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‎.github/ALL_BSP_COMPILE.json‎

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"SUB_RTT_BSP": [
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"allwinner/d1s"
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]
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},
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{
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"RTT_BSP": "novosns",
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"RTT_TOOL_CHAIN": "sourcery-arm",
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"SUB_RTT_BSP": [
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"novosns/ns800/ns800rt7p65-nssinepad"
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]
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}
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]
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}

‎bsp/novosns/ns800/README.md‎

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# NS800 BSP 说明
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NS800 系列 BSP 目前支持情况如下表所示：

‎bsp/novosns/ns800/libraries/HAL_Drivers/SConscript‎

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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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import os
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cwd = GetCurrentDir()
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src = ['drv_common.c']
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path = [cwd]
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group = SConscript(os.path.join(cwd, 'drivers', 'SConscript'))
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group = group + DefineGroup('HAL_Driver', src, depend = [''], CPPPATH = path)
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Return('group')

‎bsp/novosns/ns800/libraries/HAL_Drivers/drivers/Kconfig‎

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# comment "HAL_Drivers driver-level patch options are kept minimal; peripheral configs live in board/Kconfig"

‎bsp/novosns/ns800/libraries/HAL_Drivers/drivers/SConscript‎

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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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import os
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cwd = GetCurrentDir()
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src = []
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path = [cwd, cwd + '/config']
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if GetDepend(['BSP_USING_GPIO', 'RT_USING_PIN']):
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src += ['drv_gpio.c']
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if GetDepend(['BSP_USING_UART', 'RT_USING_SERIAL']):
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src += ['drv_uart.c']
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if GetDepend(['BSP_USING_CAN', 'RT_USING_CAN']):
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src += ['drv_can.c']
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if GetDepend(['BSP_USING_ECAP']):
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src += ['drv_ecap.c']
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group = DefineGroup('HAL_Drivers', src, depend = [''], CPPPATH = path)
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Return('group')

‎bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/adc_config.h‎

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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-06 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */
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‎bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dac_config.h‎

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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-16 thread-liu first version
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*/
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#ifndef __DAC_CONFIG_H__
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#define __DAC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_DAC1
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#ifndef DAC1_CONFIG
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#define DAC1_CONFIG \
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{ \
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.Instance = DAC1, \
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}
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#endif /* DAC2_CONFIG */
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#endif /* BSP_USING_DAC2 */
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#ifdef BSP_USING_DAC2
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#ifndef DAC2_CONFIG
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#define DAC2_CONFIG \
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{ \
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.Instance = DAC2, \
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}
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#endif /* DAC2_CONFIG */
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#endif /* BSP_USING_DAC2 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DAC_CONFIG_H__ */
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‎bsp/novosns/ns800/libraries/HAL_Drivers/drivers/config/rt7/dma_config.h‎

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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 stream0 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream0
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
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#endif
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/* DMA1 stream1 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Stream1
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#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
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#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
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#endif
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/* DMA1 stream2 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
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#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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/* DMA1 stream3 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#endif
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/* DMA1 stream4 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
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/* DMA1 stream5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
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#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
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#endif
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/* DMA1 stream6 */
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/* DMA1 stream7 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
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#endif
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#endif
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/* DMA2 stream1 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#endif
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/* DMA2 stream6 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
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#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
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#endif
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/* DMA2 stream7 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream7
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#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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