增加 FPGA 结课作业音乐播放器与电子琴 (#74)

Author: XunWei666

课程目录/FPGA/音乐播放器——电子琴/.gitignore

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+*.bak
+*.bsf
+*.qsf
+*.qws

课程目录/FPGA/音乐播放器——电子琴/PLL.bsf

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+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 152 96)
+	(text "PLL" (rect 5 0 22 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inclk0" (rect 0 0 21 12)(font "Arial" ))
+		(text "inclk0" (rect 21 27 42 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 136 32)
+		(output)
+		(text "c0" (rect 0 0 9 12)(font "Arial" ))
+		(text "c0" (rect 106 27 115 39)(font "Arial" ))
+		(line (pt 136 32)(pt 120 32)(line_width 1))
+	)
+	(port
+		(pt 136 48)
+		(output)
+		(text "c1" (rect 0 0 8 12)(font "Arial" ))
+		(text "c1" (rect 107 43 115 55)(font "Arial" ))
+		(line (pt 136 48)(pt 120 48)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 120 64)(line_width 1))
+	)
+)

课程目录/FPGA/音乐播放器——电子琴/PLL.ppf

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+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="MAX 10" variation_name="PLL" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>

课程目录/FPGA/音乐播放器——电子琴/PLL.qip

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+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "PLL.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_bb.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL.ppf"]