Validate operand type widths in emission to reject cross-width unification

The egraph uses IntExpr/FloatExpr sorts that don't distinguish SPIR-V
type widths, so i32 and i64 values can share e-classes. When extraction
picks a mismatched-width operand, the emitted instruction would violate
SPIR-V type rules (e.g. ShiftRightLogical with i32 base but i64 result).

Bail out of emission when operand width differs from result width for
same-class operations, causing the extraction loop to keep the original
instruction.

Author: LegNeato

rust/spirv-tools-opt/src/direct/emit.rs

@@ -1267,6 +1267,24 @@ fn emit_pattern(
                 synth.append(&mut s);
                 operand_ids.push(rspirv::dr::Operand::IdRef(arg_id));
             }
+            // Validate operand type widths match the result type.
+            // The egraph may unify values of different SPIR-V widths (e.g. i32
+            // and i64 are both IntExpr). When extraction picks a mismatched-width
+            // operand, the emitted instruction would be invalid. Bail out so the
+            // extraction loop keeps the original instruction.
+            let result_width = ctx.type_widths.get(&op_result_type);
+            if result_width.is_some() && result_class == operand_class {
+                for op_id in &operand_ids {
+                    if let rspirv::dr::Operand::IdRef(id) = op_id {
+                        if let Some(arg_type) = ctx.id_to_type.get(id) {
+                            let arg_width = ctx.type_widths.get(arg_type);
+                            if arg_width.is_some() && arg_width != result_width {
+                                return None;
+                            }
+                        }
+                    }
+                }
+            }
             let id = alloc_id(ctx);
             synth.push(Instruction::new(
                 opcode,