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bjorn-helgaasbjorn-helgaas
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Merge branch 'pci/misc'
- Fix typos in documentation (josh ziegler) - Use FIELD_MODIFY() instead of open-coding it (Hans Zhang) * pci/misc: PCI: Use FIELD_MODIFY() instead of open-coding it Documentation: PCI: Fix typos
2 parents e5eb703 + 42ec65b commit 2c2fb7a

21 files changed

Lines changed: 53 additions & 103 deletions

‎Documentation/PCI/pci.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -338,7 +338,7 @@ the PCI_IRQ_MSI and PCI_IRQ_MSIX flags will fail, so try to always
338338
specify PCI_IRQ_INTX as well.
339339

340340
Drivers that have different interrupt handlers for MSI/MSI-X and
341-
legacy INTx should chose the right one based on the msi_enabled
341+
legacy INTx should choose the right one based on the msi_enabled
342342
and msix_enabled flags in the pci_dev structure after calling
343343
pci_alloc_irq_vectors.
344344

‎Documentation/PCI/pciebus-howto.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ register its service with the PCI Express Port Bus driver (see
9797
section 5.2.1 & 5.2.2). It is important that a service driver
9898
initializes the pcie_port_service_driver data structure, included in
9999
header file /include/linux/pcieport_if.h, before calling these APIs.
100-
Failure to do so will result an identity mismatch, which prevents
100+
Failure to do so will result in an identity mismatch, which prevents
101101
the PCI Express Port Bus driver from loading a service driver.
102102

103103
pcie_port_service_register

‎drivers/pci/controller/dwc/pcie-al.c‎

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -253,7 +253,6 @@ static int al_pcie_config_prepare(struct al_pcie *pcie)
253253
u8 subordinate_bus;
254254
u8 secondary_bus;
255255
u32 cfg_control;
256-
u32 reg;
257256

258257
ft = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);
259258
if (!ft)
@@ -285,14 +284,9 @@ static int al_pcie_config_prepare(struct al_pcie *pcie)
285284
CFG_CONTROL;
286285

287286
cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
288-
289-
reg = cfg_control &
290-
~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
291-
292-
reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
293-
FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
294-
295-
al_pcie_controller_writel(pcie, cfg_control_offset, reg);
287+
FIELD_MODIFY(CFG_CONTROL_SUBBUS_MASK, &cfg_control, subordinate_bus);
288+
FIELD_MODIFY(CFG_CONTROL_SEC_BUS_MASK, &cfg_control, secondary_bus);
289+
al_pcie_controller_writel(pcie, cfg_control_offset, cfg_control);
296290

297291
return 0;
298292
}

‎drivers/pci/controller/dwc/pcie-designware-debugfs.c‎

Lines changed: 8 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -265,8 +265,7 @@ static ssize_t lane_detect_write(struct file *file, const char __user *buf,
265265
return ret;
266266

267267
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
268-
val &= ~(LANE_SELECT);
269-
val |= FIELD_PREP(LANE_SELECT, lane);
268+
FIELD_MODIFY(LANE_SELECT, &val, lane);
270269
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);
271270

272271
return count;
@@ -340,14 +339,10 @@ static ssize_t err_inj_write(struct file *file, const char __user *buf,
340339
val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);
341340
val |= FIELD_PREP(EINJ_COUNT, counter);
342341

343-
if (err_group == 1 || err_group == 4) {
344-
val &= ~(EINJ_VAL_DIFF);
345-
val |= FIELD_PREP(EINJ_VAL_DIFF, val_diff);
346-
}
347-
if (err_group == 4) {
348-
val &= ~(EINJ_VC_NUM);
349-
val |= FIELD_PREP(EINJ_VC_NUM, vc_num);
350-
}
342+
if (err_group == 1 || err_group == 4)
343+
FIELD_MODIFY(EINJ_VAL_DIFF, &val, val_diff);
344+
if (err_group == 4)
345+
FIELD_MODIFY(EINJ_VC_NUM, &val, vc_num);
351346

352347
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);
353348
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));
@@ -363,9 +358,8 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,
363358

364359
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
365360
val &= ~EVENT_COUNTER_ENABLE;
366-
val &= ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT);
367-
val |= FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].group_no);
368-
val |= FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].event_no);
361+
FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);
362+
FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);
369363
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
370364
}
371365

@@ -470,8 +464,7 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf,
470464
mutex_lock(&rinfo->reg_event_lock);
471465
set_event_number(pdata, pci, rinfo);
472466
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
473-
val &= ~(EVENT_COUNTER_LANE_SELECT);
474-
val |= FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane);
467+
FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);
475468
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
476469
mutex_unlock(&rinfo->reg_event_lock);
477470

‎drivers/pci/controller/dwc/pcie-designware-ep.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -708,8 +708,7 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
708708

709709
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
710710
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
711-
val &= ~PCI_MSI_FLAGS_QMASK;
712-
val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, mmc);
711+
FIELD_MODIFY(PCI_MSI_FLAGS_QMASK, &val, mmc);
713712
dw_pcie_dbi_ro_wr_en(pci);
714713
dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
715714
dw_pcie_dbi_ro_wr_dis(pci);

‎drivers/pci/controller/dwc/pcie-designware.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -937,8 +937,7 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
937937

938938
cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
939939
lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
940-
lnkcap &= ~PCI_EXP_LNKCAP_MLW;
941-
lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
940+
FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes);
942941
dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
943942
}
944943

‎drivers/pci/controller/dwc/pcie-eswin.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -211,8 +211,7 @@ static int eswin_pcie_host_init(struct dw_pcie_rp *pp)
211211

212212
/* Configure Root Port type */
213213
val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
214-
val &= ~PCIEELBI_CTRL0_DEV_TYPE;
215-
val |= FIELD_PREP(PCIEELBI_CTRL0_DEV_TYPE, PCI_EXP_TYPE_ROOT_PORT);
214+
FIELD_MODIFY(PCIEELBI_CTRL0_DEV_TYPE, &val, PCI_EXP_TYPE_ROOT_PORT);
216215
writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
217216

218217
list_for_each_entry(port, &pcie->ports, list) {

‎drivers/pci/controller/dwc/pcie-nxp-s32g.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -139,8 +139,7 @@ static int s32g_init_pcie_controller(struct dw_pcie_rp *pp)
139139

140140
/* Set RP mode */
141141
val = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1);
142-
val &= ~DEVICE_TYPE_MASK;
143-
val |= FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
142+
FIELD_MODIFY(DEVICE_TYPE_MASK, &val, PCI_EXP_TYPE_ROOT_PORT);
144143

145144
/* Use default CRNS */
146145
val &= ~SRIS_MODE;

‎drivers/pci/controller/dwc/pcie-qcom-common.c‎

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -30,20 +30,15 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
3030

3131
reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
3232
reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
33-
reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
34-
reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
35-
speed - PCIE_SPEED_8_0GT);
33+
FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, &reg,
34+
speed - PCIE_SPEED_8_0GT);
3635
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
3736

3837
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
39-
reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
40-
GEN3_EQ_FMDC_N_EVALS |
41-
GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |
42-
GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);
43-
reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
44-
FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
45-
FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |
46-
FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);
38+
FIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, &reg, 0x1);
39+
FIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, &reg, 0xd);
40+
FIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, &reg, 0x5);
41+
FIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, &reg, 0x5);
4742
dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
4843

4944
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
@@ -61,28 +56,21 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
6156
u32 reg;
6257

6358
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
64-
reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
65-
MARGINING_NUM_VOLTAGE_STEPS |
66-
MARGINING_MAX_TIMING_OFFSET |
67-
MARGINING_NUM_TIMING_STEPS);
68-
reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
69-
FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
70-
FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
71-
FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
59+
FIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, &reg, 0x24);
60+
FIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, &reg, 0x78);
61+
FIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, &reg, 0x32);
62+
FIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, &reg, 0x10);
7263
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
7364

7465
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
7566
reg |= MARGINING_IND_ERROR_SAMPLER |
7667
MARGINING_SAMPLE_REPORTING_METHOD |
7768
MARGINING_IND_LEFT_RIGHT_TIMING |
7869
MARGINING_VOLTAGE_SUPPORTED;
79-
reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
80-
MARGINING_MAXLANES |
81-
MARGINING_SAMPLE_RATE_TIMING |
82-
MARGINING_SAMPLE_RATE_VOLTAGE);
83-
reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
84-
FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
85-
FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
70+
reg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;
71+
FIELD_MODIFY(MARGINING_MAXLANES, &reg, pci->num_lanes);
72+
FIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, &reg, 0x3f);
73+
FIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, &reg, 0x3f);
8674
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
8775
}
8876
EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);

‎drivers/pci/controller/dwc/pcie-qcom-ep.c‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -494,15 +494,13 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
494494
/* Set the L0s Exit Latency to 2us-4us = 0x6 */
495495
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
496496
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
497-
val &= ~PCI_EXP_LNKCAP_L0SEL;
498-
val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
497+
FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6);
499498
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
500499

501500
/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
502501
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
503502
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
504-
val &= ~PCI_EXP_LNKCAP_L1EL;
505-
val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
503+
FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6);
506504
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
507505

508506
dw_pcie_dbi_ro_wr_dis(pci);

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