Merge commit from fork

* cmov: add regressions tests for aarch64 Cmov/CmovEq

* cmov: fix aarch64 Cmov not ignoring high bits of condition

* cmov: fix aarch64 CmovEq not ignoring high bits

Author: robinhundt

cmov/src/backends/aarch64.rs

@@ -3,10 +3,10 @@ use core::arch::asm;
 
 /// Conditional select
 macro_rules! csel {
-    ($cmp:expr, $csel:expr, $dst:expr, $src:expr, $condition:expr) => {
+    ($tst:expr, $csel:expr, $dst:expr, $src:expr, $condition:expr) => {
         unsafe {
             asm! {
-                "cmp {0:w}, 0",
+                $tst,
                 $csel,
                 in(reg) $condition,
                 inlateout(reg) *$dst,
@@ -45,14 +45,30 @@ macro_rules! cseleq {
 /// Conditional select using 32-bit `:w` registers
 macro_rules! csel32 {
     ($csel:expr, $dst:expr, $src:expr, $condition:expr) => {
-        csel!("cmp {0:w}, 0", $csel, $dst, $src, $condition)
+        csel!("tst {0:w}, 0xff", $csel, $dst, $src, $condition)
     };
 }
 
 /// Conditional select using 64-bit `:x` registers
 macro_rules! csel64 {
     ($csel:expr, $dst:expr, $src:expr, $condition:expr) => {
-        csel!("cmp {0:x}, 0", $csel, $dst, $src, $condition)
+        csel!("tst {0:x}, 0xff", $csel, $dst, $src, $condition)
+    };
+}
+
+/// Conditional select equality test using 32-bit `:w` registers and 
+/// correctly handling unspecified upper bits of 16 bit inputs
+macro_rules! cseleq16 {
+    ($instruction:expr, $lhs:expr, $rhs:expr, $condition:expr, $dst:expr) => {
+        cseleq!(
+            "eor {0:w}, {1:w}, {2:w}",
+            "tst {0:w}, 0xffff",
+            $instruction,
+            $lhs,
+            $rhs,
+            $condition,
+            $dst
+        )
     };
 }
 
@@ -129,12 +145,12 @@ impl Cmov for u64 {
 impl CmovEq for u16 {
     #[inline]
     fn cmovne(&self, rhs: &Self, input: Condition, output: &mut Condition) {
-        cseleq32!("csel {3:w}, {4:w}, {5:w}, NE", self, rhs, input, output);
+        cseleq16!("csel {3:w}, {4:w}, {5:w}, NE", self, rhs, input, output);
     }
 
     #[inline]
     fn cmoveq(&self, rhs: &Self, input: Condition, output: &mut Condition) {
-        cseleq32!("csel {3:w}, {4:w}, {5:w}, EQ", self, rhs, input, output);
+        cseleq16!("csel {3:w}, {4:w}, {5:w}, EQ", self, rhs, input, output);
     }
 }
 

cmov/tests/regression.rs

@@ -1,6 +1,8 @@
 //! Tests for previous bugs in the implementation.
 
-use cmov::CmovEq;
+use std::hint::black_box;
+
+use cmov::{Cmov, CmovEq};
 
 #[test]
 fn u64_cmoveq() {
@@ -11,3 +13,37 @@ fn u64_cmoveq() {
     // 0x8200_0000_0000_0000 is not equal to 0
     assert_eq!(cond, 0);
 }
+
+#[test]
+fn cmovz_wrong_output() {
+    // The black box is necessary here, as otherwise the compiler will
+    // provide a constant 0 to the csel
+    let condition: u32 = black_box(1 << 8);
+    let mut left = 1;
+    let right = 2;
+    debug_assert_eq!(0, condition as u8);
+    left.cmovz(&right, condition as u8);
+    assert_eq!(left, right);
+}
+
+#[test]
+fn cmoveq_wrong_output_u16() {
+    let input = 1;
+    let mut output = 0;
+    let left: u32 = black_box(1 << 16);
+    let right: u32 = black_box(1 << 17);
+    debug_assert_eq!(left as u16, right as u16);
+    (left as u16).cmoveq(&(right as u16), input, &mut output);
+    assert_eq!(input, output);
+}
+
+#[test]
+fn cmoveq_wrong_output_i16() {
+    let input = 1;
+    let mut output = 0;
+    let left: u32 = black_box(1 << 16);
+    let right: u32 = black_box(1 << 17);
+    debug_assert_eq!(left as i16, right as i16);
+    (left as i16).cmoveq(&(right as i16), input, &mut output);
+    assert_eq!(input, output);
+}