From 1a59ead95958f4ce1d39400a86ccead17ba93a23 Mon Sep 17 00:00:00 2001 From: Tony Arcieri Date: Fri, 12 Jun 2026 12:24:37 -0600 Subject: [PATCH] zeroize: always enable AVX-512 support It was previously gated under the `simd` feature due to MSRV 1.72. Since we're now MSRV 1.85, it can always be enabled. --- zeroize/Cargo.toml | 2 +- zeroize/src/x86.rs | 9 +++------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/zeroize/Cargo.toml b/zeroize/Cargo.toml index a8e0d4ea..379b7ca5 100644 --- a/zeroize/Cargo.toml +++ b/zeroize/Cargo.toml @@ -29,7 +29,7 @@ std = ["alloc"] aarch64 = [] # NOTE: vestigial no-op feature; AArch64 support is always enabled now derive = ["zeroize_derive"] -simd = [] # NOTE: MSRV 1.72 +simd = [] # NOTE: vestigial no-op feature; always enabled [lints] workspace = true diff --git a/zeroize/src/x86.rs b/zeroize/src/x86.rs index cbaf7367..b3a40708 100644 --- a/zeroize/src/x86.rs +++ b/zeroize/src/x86.rs @@ -4,7 +4,6 @@ use crate::{Zeroize, optimization_barrier, volatile_write}; #[cfg(target_arch = "x86")] use core::arch::x86::*; - #[cfg(target_arch = "x86_64")] use core::arch::x86_64::*; @@ -22,8 +21,6 @@ macro_rules! impl_zeroize_for_simd_register { }; } -impl_zeroize_for_simd_register!(__m128, __m128d, __m128i, __m256, __m256d, __m256i); - -// NOTE: MSRV 1.72 -#[cfg(feature = "simd")] -impl_zeroize_for_simd_register!(__m512, __m512d, __m512i); +impl_zeroize_for_simd_register!( + __m128, __m128d, __m128i, __m256, __m256d, __m256i, __m512, __m512d, __m512i +);