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Mohamed IssaDerek White
Mohamed Issa
authored and
Derek White
committed
8378295: Update scalar AVX10 floating point min/max definitions
Backport-of: 1a99655
1 parent 9415624 commit 8434cb7

11 files changed

Lines changed: 626 additions & 321 deletions

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‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 94 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -3472,22 +3472,52 @@ void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
34723472
emit_int16(0x6F, (0xC0 | encode));
34733473
}
34743474

3475-
void Assembler::vmovw(XMMRegister dst, Register src) {
3475+
void Assembler::evmovw(XMMRegister dst, Register src) {
34763476
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
34773477
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
34783478
attributes.set_is_evex_instruction();
34793479
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes, true);
34803480
emit_int16(0x6E, (0xC0 | encode));
34813481
}
34823482

3483-
void Assembler::vmovw(Register dst, XMMRegister src) {
3483+
void Assembler::evmovw(Register dst, XMMRegister src) {
34843484
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
34853485
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
34863486
attributes.set_is_evex_instruction();
34873487
int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_MAP5, &attributes, true);
34883488
emit_int16(0x7E, (0xC0 | encode));
34893489
}
34903490

3491+
void Assembler::evmovw(XMMRegister dst, Address src) {
3492+
assert(VM_Version::supports_avx10_2(), "");
3493+
InstructionMark im(this);
3494+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3495+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3496+
attributes.set_is_evex_instruction();
3497+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3498+
emit_int8(0x6E);
3499+
emit_operand(dst, src, 0);
3500+
}
3501+
3502+
void Assembler::evmovw(Address dst, XMMRegister src) {
3503+
assert(VM_Version::supports_avx10_2(), "");
3504+
InstructionMark im(this);
3505+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3506+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3507+
attributes.set_is_evex_instruction();
3508+
vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3509+
emit_int8(0x7E);
3510+
emit_operand(src, dst, 0);
3511+
}
3512+
3513+
void Assembler::evmovw(XMMRegister dst, XMMRegister src) {
3514+
assert(VM_Version::supports_avx10_2(), "");
3515+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3516+
attributes.set_is_evex_instruction();
3517+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
3518+
emit_int16(0x6E, (0xC0 | encode));
3519+
}
3520+
34913521
void Assembler::vmovdqu(XMMRegister dst, Address src) {
34923522
assert(UseAVX > 0, "");
34933523
InstructionMark im(this);
@@ -7303,6 +7333,42 @@ void Assembler::etzcntq(Register dst, Address src, bool no_flags) {
73037333
emit_operand(dst, src, 0);
73047334
}
73057335

7336+
void Assembler::evucomish(XMMRegister dst, Address src) {
7337+
InstructionMark im(this);
7338+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7339+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7340+
attributes.set_is_evex_instruction();
7341+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
7342+
emit_int8(0x2E);
7343+
emit_operand(dst, src, 0);
7344+
}
7345+
7346+
void Assembler::evucomish(XMMRegister dst, XMMRegister src) {
7347+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7348+
attributes.set_is_evex_instruction();
7349+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_MAP5, &attributes);
7350+
emit_int16(0x2E, (0xC0 | encode));
7351+
}
7352+
7353+
void Assembler::evucomxsh(XMMRegister dst, Address src) {
7354+
assert(VM_Version::supports_avx10_2(), "");
7355+
InstructionMark im(this);
7356+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7357+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7358+
attributes.set_is_evex_instruction();
7359+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
7360+
emit_int8(0x2E);
7361+
emit_operand(dst, src, 0);
7362+
}
7363+
7364+
void Assembler::evucomxsh(XMMRegister dst, XMMRegister src) {
7365+
assert(VM_Version::supports_avx10_2(), "");
7366+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7367+
attributes.set_is_evex_instruction();
7368+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
7369+
emit_int16(0x2E, (0xC0 | encode));
7370+
}
7371+
73067372
void Assembler::ucomisd(XMMRegister dst, Address src) {
73077373
InstructionMark im(this);
73087374
InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7320,7 +7386,7 @@ void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
73207386
emit_int16(0x2E, (0xC0 | encode));
73217387
}
73227388

7323-
void Assembler::vucomxsd(XMMRegister dst, Address src) {
7389+
void Assembler::evucomxsd(XMMRegister dst, Address src) {
73247390
assert(VM_Version::supports_avx10_2(), "");
73257391
InstructionMark im(this);
73267392
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7331,7 +7397,7 @@ void Assembler::vucomxsd(XMMRegister dst, Address src) {
73317397
emit_operand(dst, src, 0);
73327398
}
73337399

7334-
void Assembler::vucomxsd(XMMRegister dst, XMMRegister src) {
7400+
void Assembler::evucomxsd(XMMRegister dst, XMMRegister src) {
73357401
assert(VM_Version::supports_avx10_2(), "");
73367402
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
73377403
attributes.set_is_evex_instruction();
@@ -7354,7 +7420,7 @@ void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
73547420
emit_int16(0x2E, (0xC0 | encode));
73557421
}
73567422

7357-
void Assembler::vucomxss(XMMRegister dst, Address src) {
7423+
void Assembler::evucomxss(XMMRegister dst, Address src) {
73587424
assert(VM_Version::supports_avx10_2(), "");
73597425
InstructionMark im(this);
73607426
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7365,7 +7431,7 @@ void Assembler::vucomxss(XMMRegister dst, Address src) {
73657431
emit_operand(dst, src, 0);
73667432
}
73677433

7368-
void Assembler::vucomxss(XMMRegister dst, XMMRegister src) {
7434+
void Assembler::evucomxss(XMMRegister dst, XMMRegister src) {
73697435
assert(VM_Version::supports_avx10_2(), "");
73707436
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
73717437
attributes.set_is_evex_instruction();
@@ -8404,30 +8470,6 @@ void Assembler::vmulsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
84048470
emit_int16(0x59, (0xC0 | encode));
84058471
}
84068472

8407-
void Assembler::vmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8408-
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
8409-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8410-
attributes.set_is_evex_instruction();
8411-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
8412-
emit_int16(0x5F, (0xC0 | encode));
8413-
}
8414-
8415-
void Assembler::eminmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
8416-
assert(VM_Version::supports_avx10_2(), "");
8417-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8418-
attributes.set_is_evex_instruction();
8419-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
8420-
emit_int24(0x53, (0xC0 | encode), imm8);
8421-
}
8422-
8423-
void Assembler::vminsh(XMMRegister dst, XMMRegister nds, XMMRegister src) {
8424-
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
8425-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8426-
attributes.set_is_evex_instruction();
8427-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_MAP5, &attributes);
8428-
emit_int16(0x5D, (0xC0 | encode));
8429-
}
8430-
84318473
void Assembler::vsqrtsh(XMMRegister dst, XMMRegister src) {
84328474
assert(VM_Version::supports_avx512_fp16(), "requires AVX512-FP16");
84338475
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -13362,48 +13404,38 @@ bool Assembler::is_demotable(bool no_flags, int dst_enc, int nds_enc) {
1336213404
return (!no_flags && dst_enc == nds_enc);
1336313405
}
1336413406

13365-
void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13366-
assert(VM_Version::supports_avx(), "");
13367-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13368-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13369-
emit_int16(0x5F, (0xC0 | encode));
13370-
}
13371-
13372-
void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13373-
assert(VM_Version::supports_avx(), "");
13374-
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13375-
attributes.set_rex_vex_w_reverted();
13376-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13377-
emit_int16(0x5F, (0xC0 | encode));
13378-
}
13379-
13380-
void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13381-
assert(VM_Version::supports_avx(), "");
13382-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13383-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13384-
emit_int16(0x5D, (0xC0 | encode));
13407+
void Assembler::evminmaxsh(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
13408+
assert(VM_Version::supports_avx10_2(), "");
13409+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
13410+
attributes.set_is_evex_instruction();
13411+
attributes.set_embedded_opmask_register_specifier(mask);
13412+
if (merge) {
13413+
attributes.reset_is_clear_context();
13414+
}
13415+
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
13416+
emit_int24(0x53, (0xC0 | encode), imm8);
1338513417
}
1338613418

13387-
void Assembler::eminmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
13419+
void Assembler::evminmaxss(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
1338813420
assert(VM_Version::supports_avx10_2(), "");
13389-
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13421+
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1339013422
attributes.set_is_evex_instruction();
13423+
attributes.set_embedded_opmask_register_specifier(mask);
13424+
if (merge) {
13425+
attributes.reset_is_clear_context();
13426+
}
1339113427
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1339213428
emit_int24(0x53, (0xC0 | encode), imm8);
1339313429
}
1339413430

13395-
void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
13396-
assert(VM_Version::supports_avx(), "");
13397-
InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13398-
attributes.set_rex_vex_w_reverted();
13399-
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13400-
emit_int16(0x5D, (0xC0 | encode));
13401-
}
13402-
13403-
void Assembler::eminmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
13431+
void Assembler::evminmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8) {
1340413432
assert(VM_Version::supports_avx10_2(), "");
13405-
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13433+
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1340613434
attributes.set_is_evex_instruction();
13435+
attributes.set_embedded_opmask_register_specifier(mask);
13436+
if (merge) {
13437+
attributes.reset_is_clear_context();
13438+
}
1340713439
int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1340813440
emit_int24(0x53, (0xC0 | encode), imm8);
1340913441
}

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1694,8 +1694,11 @@ class Assembler : public AbstractAssembler {
16941694
void movsbl(Register dst, Address src);
16951695
void movsbl(Register dst, Register src);
16961696

1697-
void vmovw(XMMRegister dst, Register src);
1698-
void vmovw(Register dst, XMMRegister src);
1697+
void evmovw(XMMRegister dst, Register src);
1698+
void evmovw(Register dst, XMMRegister src);
1699+
void evmovw(XMMRegister dst, Address src);
1700+
void evmovw(Address dst, XMMRegister src);
1701+
void evmovw(XMMRegister dst, XMMRegister src);
16991702

17001703
void movsbq(Register dst, Address src);
17011704
void movsbq(Register dst, Register src);
@@ -2328,17 +2331,23 @@ class Assembler : public AbstractAssembler {
23282331
void tzcntq(Register dst, Address src);
23292332
void etzcntq(Register dst, Address src, bool no_flags);
23302333

2334+
// Unordered Compare Scalar Half-Precision Floating-Point Values and set EFLAGS
2335+
void evucomish(XMMRegister dst, Address src);
2336+
void evucomish(XMMRegister dst, XMMRegister src);
2337+
void evucomxsh(XMMRegister dst, Address src);
2338+
void evucomxsh(XMMRegister dst, XMMRegister src);
2339+
23312340
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
23322341
void ucomisd(XMMRegister dst, Address src);
23332342
void ucomisd(XMMRegister dst, XMMRegister src);
2334-
void vucomxsd(XMMRegister dst, Address src);
2335-
void vucomxsd(XMMRegister dst, XMMRegister src);
2343+
void evucomxsd(XMMRegister dst, Address src);
2344+
void evucomxsd(XMMRegister dst, XMMRegister src);
23362345

23372346
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
23382347
void ucomiss(XMMRegister dst, Address src);
23392348
void ucomiss(XMMRegister dst, XMMRegister src);
2340-
void vucomxss(XMMRegister dst, Address src);
2341-
void vucomxss(XMMRegister dst, XMMRegister src);
2349+
void evucomxss(XMMRegister dst, Address src);
2350+
void evucomxss(XMMRegister dst, XMMRegister src);
23422351

23432352
void xabort(int8_t imm8);
23442353

@@ -2416,11 +2425,6 @@ class Assembler : public AbstractAssembler {
24162425
void vsubss(XMMRegister dst, XMMRegister nds, Address src);
24172426
void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
24182427

2419-
void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2420-
void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2421-
void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2422-
void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2423-
24242428
void sarxl(Register dst, Register src1, Register src2);
24252429
void sarxl(Register dst, Address src1, Register src2);
24262430
void sarxq(Register dst, Register src1, Register src2);
@@ -2551,8 +2555,6 @@ class Assembler : public AbstractAssembler {
25512555
void vsubsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25522556
void vmulsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25532557
void vdivsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
2554-
void vmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
2555-
void vminsh(XMMRegister dst, XMMRegister nds, XMMRegister src);
25562558
void vsqrtsh(XMMRegister dst, XMMRegister src);
25572559
void vfmadd132sh(XMMRegister dst, XMMRegister src1, XMMRegister src2);
25582560

@@ -2789,9 +2791,9 @@ class Assembler : public AbstractAssembler {
27892791
void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
27902792

27912793
// AVX10.2 floating point minmax instructions
2792-
void eminmaxsh(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2793-
void eminmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2794-
void eminmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
2794+
void evminmaxsh(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
2795+
void evminmaxss(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
2796+
void evminmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8);
27952797
void evminmaxph(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8, int vector_len);
27962798
void evminmaxph(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int imm8, int vector_len);
27972799
void evminmaxps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int imm8, int vector_len);

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