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iklamiklam
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8383542: Remove hard-coded enum value from CPU_FEATURE_FLAGS
Reviewed-by: kvn, asmehra, adinn
1 parent 69455d5 commit 855d591

8 files changed

Lines changed: 143 additions & 165 deletions

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‎src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@
4141

4242
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant)
4343

44-
#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
44+
#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
4545
#define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT)
4646

4747
#endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP

‎src/hotspot/cpu/aarch64/vm_version_aarch64.cpp‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,9 @@ bool VM_Version::_cache_dic_enabled;
5757
bool VM_Version::_cache_idc_enabled;
5858
bool VM_Version::_ic_ivau_trapped;
5959

60-
const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
60+
#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
61+
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
62+
#undef DECLARE_CPU_FEATURE_NAME
6163

6264
static SpinWait get_spin_wait_desc() {
6365
SpinWait spin_wait(OnSpinWaitInst, OnSpinWaitInstCount, OnSpinWaitDelay);
@@ -104,11 +106,6 @@ static bool has_neoverse_n1_errata_1542419() {
104106
}
105107

106108
void VM_Version::initialize() {
107-
#define SET_CPU_FEATURE_NAME(id, name, bit) \
108-
_features_names[bit] = XSTR(name);
109-
CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
110-
#undef SET_CPU_FEATURE_NAME
111-
112109
_supports_atomic_getset4 = true;
113110
_supports_atomic_getadd4 = true;
114111
_supports_atomic_getset8 = true;

‎src/hotspot/cpu/aarch64/vm_version_aarch64.hpp‎

Lines changed: 26 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -144,44 +144,43 @@ class VM_Version : public Abstract_VM_Version {
144144
CPU_MODEL_ARM_NEOVERSE_N3 = 0xd8e,
145145
};
146146

147-
#define CPU_FEATURE_FLAGS(decl) \
148-
decl(FP, fp, 0) \
149-
decl(ASIMD, asimd, 1) \
150-
decl(EVTSTRM, evtstrm, 2) \
151-
decl(AES, aes, 3) \
152-
decl(PMULL, pmull, 4) \
153-
decl(SHA1, sha1, 5) \
154-
decl(SHA2, sha256, 6) \
155-
decl(CRC32, crc32, 7) \
156-
decl(LSE, lse, 8) \
157-
decl(FPHP, fphp, 9) \
158-
decl(ASIMDHP, asimdhp, 10) \
159-
decl(DCPOP, dcpop, 16) \
160-
decl(SHA3, sha3, 17) \
161-
decl(SHA512, sha512, 21) \
162-
decl(SVE, sve, 22) \
163-
decl(SB, sb, 29) \
164-
decl(PACA, paca, 30) \
165-
/* flags above must follow Linux HWCAP */ \
166-
decl(SVEBITPERM, svebitperm, 27) \
167-
decl(SVE2, sve2, 28) \
168-
decl(A53MAC, a53mac, 31) \
169-
decl(ECV, ecv, 32) \
170-
decl(WFXT, wfxt, 33)
147+
#define CPU_FEATURE_FLAGS(decl) \
148+
decl(FP, fp ) \
149+
decl(ASIMD, asimd ) \
150+
decl(EVTSTRM, evtstrm ) \
151+
decl(AES, aes ) \
152+
decl(PMULL, pmull ) \
153+
decl(SHA1, sha1 ) \
154+
decl(SHA2, sha256 ) \
155+
decl(CRC32, crc32 ) \
156+
decl(LSE, lse ) \
157+
decl(FPHP, fphp ) \
158+
decl(ASIMDHP, asimdhp ) \
159+
decl(DCPOP, dcpop ) \
160+
decl(SHA3, sha3 ) \
161+
decl(SHA512, sha512 ) \
162+
decl(SVE, sve ) \
163+
decl(SB, sb ) \
164+
decl(PACA, paca ) \
165+
decl(SVEBITPERM, svebitperm ) \
166+
decl(SVE2, sve2 ) \
167+
decl(A53MAC, a53mac ) \
168+
decl(ECV, ecv ) \
169+
decl(WFXT, wfxt )
171170

172171
enum Feature_Flag {
173-
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = bit,
172+
#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id,
174173
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
175174
#undef DECLARE_CPU_FEATURE_FLAG
176175
MAX_CPU_FEATURES
177176
};
178177

179178
STATIC_ASSERT(sizeof(_features) * BitsPerByte >= MAX_CPU_FEATURES);
180179

181-
static const char* _features_names[MAX_CPU_FEATURES];
180+
static const char* _features_names[];
182181

183182
// Feature identification
184-
#define CPU_FEATURE_DETECTION(id, name, bit) \
183+
#define CPU_FEATURE_DETECTION(id, name) \
185184
static bool supports_##name() { return supports_feature(CPU_##id); }
186185
CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
187186
#undef CPU_FEATURE_DETECTION

‎src/hotspot/cpu/x86/vmStructs_x86.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@
4646

4747
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant)
4848

49-
#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
49+
#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
5050
#define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT)
5151

5252
#endif // CPU_X86_VMSTRUCTS_X86_HPP

‎src/hotspot/cpu/x86/vm_version_x86.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ int VM_Version::_stepping;
4848
bool VM_Version::_has_intel_jcc_erratum;
4949
VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
5050

51-
#define DECLARE_CPU_FEATURE_NAME(id, name, bit) XSTR(name),
51+
#define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
5252
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
5353
#undef DECLARE_CPU_FEATURE_NAME
5454

‎src/hotspot/cpu/x86/vm_version_x86.hpp‎

Lines changed: 80 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -377,86 +377,86 @@ class VM_Version : public Abstract_VM_Version {
377377
*/
378378
enum Feature_Flag {
379379
#define CPU_FEATURE_FLAGS(decl) \
380-
decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \
381-
decl(CMOV, cmov, 1) \
382-
decl(FXSR, fxsr, 2) \
383-
decl(HT, ht, 3) \
384-
\
385-
decl(MMX, mmx, 4) \
386-
decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
387-
/* may not necessarily support other 3dnow instructions */ \
388-
decl(SSE, sse, 6) \
389-
decl(SSE2, sse2, 7) \
390-
\
391-
decl(SSE3, sse3, 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
392-
decl(SSSE3, ssse3, 9 ) \
393-
decl(SSE4A, sse4a, 10) \
394-
decl(SSE4_1, sse4.1, 11) \
395-
\
396-
decl(SSE4_2, sse4.2, 12) \
397-
decl(POPCNT, popcnt, 13) \
398-
decl(LZCNT, lzcnt, 14) \
399-
decl(TSC, tsc, 15) \
400-
\
401-
decl(TSCINV_BIT, tscinvbit, 16) \
402-
decl(TSCINV, tscinv, 17) \
403-
decl(AVX, avx, 18) \
404-
decl(AVX2, avx2, 19) \
405-
\
406-
decl(AES, aes, 20) \
407-
decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \
408-
decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \
409-
decl(BMI1, bmi1, 23) \
410-
\
411-
decl(BMI2, bmi2, 24) \
412-
decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \
413-
decl(ADX, adx, 26) \
414-
decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \
415-
\
416-
decl(AVX512DQ, avx512dq, 28) \
417-
decl(AVX512PF, avx512pf, 29) \
418-
decl(AVX512ER, avx512er, 30) \
419-
decl(AVX512CD, avx512cd, 31) \
420-
\
421-
decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \
422-
decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \
423-
decl(SHA, sha, 34) /* SHA instructions */ \
424-
decl(FMA, fma, 35) /* FMA instructions */ \
425-
\
426-
decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \
427-
decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \
428-
decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \
429-
decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \
430-
\
431-
decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \
432-
decl(FLUSH, clflush, 41) /* flush instruction */ \
433-
decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \
434-
decl(CLWB, clwb, 43) /* clwb instruction */ \
435-
\
436-
decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \
437-
decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \
438-
decl(HV, hv, 46) /* Hypervisor instructions */ \
439-
decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \
440-
decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \
441-
decl(RDPID, rdpid, 49) /* RDPID instruction */ \
442-
decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \
443-
decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \
444-
decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\
445-
decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \
446-
decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \
447-
decl(OSPKE, ospke, 55) /* OS enables protection keys */ \
448-
decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
449-
decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \
450-
decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \
451-
decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
452-
decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \
453-
decl(SHA512, sha512, 61) /* SHA512 instructions*/ \
454-
decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \
455-
decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
456-
decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
457-
decl(HYBRID, hybrid, 65) /* Hybrid architecture */
458-
459-
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
380+
decl(CX8, cx8 ) /* next bits are from cpuid 1 (EDX) */ \
381+
decl(CMOV, cmov ) \
382+
decl(FXSR, fxsr ) \
383+
decl(HT, ht ) \
384+
\
385+
decl(MMX, mmx ) \
386+
decl(3DNOW_PREFETCH, 3dnowpref ) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
387+
/* may not necessarily support other 3dnow instructions */ \
388+
decl(SSE, sse ) \
389+
decl(SSE2, sse2 ) \
390+
\
391+
decl(SSE3, sse3 ) /* SSE3 comes from cpuid 1 (ECX) */ \
392+
decl(SSSE3, ssse3 ) \
393+
decl(SSE4A, sse4a ) \
394+
decl(SSE4_1, sse4.1 ) \
395+
\
396+
decl(SSE4_2, sse4.2 ) \
397+
decl(POPCNT, popcnt ) \
398+
decl(LZCNT, lzcnt ) \
399+
decl(TSC, tsc ) \
400+
\
401+
decl(TSCINV_BIT, tscinvbit ) \
402+
decl(TSCINV, tscinv ) \
403+
decl(AVX, avx ) \
404+
decl(AVX2, avx2 ) \
405+
\
406+
decl(AES, aes ) \
407+
decl(ERMS, erms ) /* enhanced 'rep movsb/stosb' instructions */ \
408+
decl(CLMUL, clmul ) /* carryless multiply for CRC */ \
409+
decl(BMI1, bmi1 ) \
410+
\
411+
decl(BMI2, bmi2 ) \
412+
decl(RTM, rtm ) /* Restricted Transactional Memory instructions */ \
413+
decl(ADX, adx ) \
414+
decl(AVX512F, avx512f ) /* AVX 512bit foundation instructions */ \
415+
\
416+
decl(AVX512DQ, avx512dq ) \
417+
decl(AVX512PF, avx512pf ) \
418+
decl(AVX512ER, avx512er ) \
419+
decl(AVX512CD, avx512cd ) \
420+
\
421+
decl(AVX512BW, avx512bw ) /* Byte and word vector instructions */ \
422+
decl(AVX512VL, avx512vl ) /* EVEX instructions with smaller vector length */ \
423+
decl(SHA, sha ) /* SHA instructions */ \
424+
decl(FMA, fma ) /* FMA instructions */ \
425+
\
426+
decl(VZEROUPPER, vzeroupper ) /* Vzeroupper instruction */ \
427+
decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq ) /* Vector popcount */ \
428+
decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq ) /* Vector carryless multiplication */ \
429+
decl(AVX512_VAES, avx512_vaes ) /* Vector AES instruction */ \
430+
\
431+
decl(AVX512_VNNI, avx512_vnni ) /* Vector Neural Network Instructions */ \
432+
decl(FLUSH, clflush ) /* flush instruction */ \
433+
decl(FLUSHOPT, clflushopt ) /* flusopth instruction */ \
434+
decl(CLWB, clwb ) /* clwb instruction */ \
435+
\
436+
decl(AVX512_VBMI2, avx512_vbmi2 ) /* VBMI2 shift left double instructions */ \
437+
decl(AVX512_VBMI, avx512_vbmi ) /* Vector BMI instructions */ \
438+
decl(HV, hv ) /* Hypervisor instructions */ \
439+
decl(SERIALIZE, serialize ) /* CPU SERIALIZE */ \
440+
decl(RDTSCP, rdtscp ) /* RDTSCP instruction */ \
441+
decl(RDPID, rdpid ) /* RDPID instruction */ \
442+
decl(FSRM, fsrm ) /* Fast Short REP MOV */ \
443+
decl(GFNI, gfni ) /* Vector GFNI instructions */ \
444+
decl(AVX512_BITALG, avx512_bitalg ) /* Vector sub-word popcount and bit gather instructions */\
445+
decl(F16C, f16c ) /* Half-precision and single precision FP conversion instructions*/ \
446+
decl(PKU, pku ) /* Protection keys for user-mode pages */ \
447+
decl(OSPKE, ospke ) /* OS enables protection keys */ \
448+
decl(CET_IBT, cet_ibt ) /* Control Flow Enforcement - Indirect Branch Tracking */ \
449+
decl(CET_SS, cet_ss ) /* Control Flow Enforcement - Shadow Stack */ \
450+
decl(AVX512_IFMA, avx512_ifma ) /* Integer Vector FMA instructions*/ \
451+
decl(AVX_IFMA, avx_ifma ) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
452+
decl(APX_F, apx_f ) /* Intel Advanced Performance Extensions*/ \
453+
decl(SHA512, sha512 ) /* SHA512 instructions*/ \
454+
decl(AVX512_FP16, avx512_fp16 ) /* AVX512 FP16 ISA support*/ \
455+
decl(AVX10_1, avx10_1 ) /* AVX10 512 bit vector ISA Version 1 support*/ \
456+
decl(AVX10_2, avx10_2 ) /* AVX10 512 bit vector ISA Version 2 support*/ \
457+
decl(HYBRID, hybrid ) /* Hybrid architecture */
458+
459+
#define DECLARE_CPU_FEATURE_FLAG(id, name) CPU_##id,
460460
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
461461
#undef DECLARE_CPU_FEATURE_FLAG
462462
MAX_CPU_FEATURES

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