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Mohamed IssaDerek White
Mohamed Issa
authored and
Derek White
committed
8371955: Support AVX10 floating point comparison instructions
Reviewed-by: sviswanathan, drwhite, shade Backport-of: 161aa5d
1 parent 91f3611 commit 9415624

10 files changed

Lines changed: 904 additions & 204 deletions

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‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -7320,6 +7320,25 @@ void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
73207320
emit_int16(0x2E, (0xC0 | encode));
73217321
}
73227322

7323+
void Assembler::vucomxsd(XMMRegister dst, Address src) {
7324+
assert(VM_Version::supports_avx10_2(), "");
7325+
InstructionMark im(this);
7326+
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7327+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7328+
attributes.set_is_evex_instruction();
7329+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7330+
emit_int8(0x2E);
7331+
emit_operand(dst, src, 0);
7332+
}
7333+
7334+
void Assembler::vucomxsd(XMMRegister dst, XMMRegister src) {
7335+
assert(VM_Version::supports_avx10_2(), "");
7336+
InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7337+
attributes.set_is_evex_instruction();
7338+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7339+
emit_int16(0x2E, (0xC0 | encode));
7340+
}
7341+
73237342
void Assembler::ucomiss(XMMRegister dst, Address src) {
73247343
InstructionMark im(this);
73257344
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
@@ -7335,6 +7354,25 @@ void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
73357354
emit_int16(0x2E, (0xC0 | encode));
73367355
}
73377356

7357+
void Assembler::vucomxss(XMMRegister dst, Address src) {
7358+
assert(VM_Version::supports_avx10_2(), "");
7359+
InstructionMark im(this);
7360+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7361+
attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7362+
attributes.set_is_evex_instruction();
7363+
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7364+
emit_int8(0x2E);
7365+
emit_operand(dst, src, 0);
7366+
}
7367+
7368+
void Assembler::vucomxss(XMMRegister dst, XMMRegister src) {
7369+
assert(VM_Version::supports_avx10_2(), "");
7370+
InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7371+
attributes.set_is_evex_instruction();
7372+
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7373+
emit_int16(0x2E, (0xC0 | encode));
7374+
}
7375+
73387376
void Assembler::xabort(int8_t imm8) {
73397377
emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF));
73407378
}

‎src/hotspot/cpu/x86/assembler_x86.hpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -2331,10 +2331,14 @@ class Assembler : public AbstractAssembler {
23312331
// Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
23322332
void ucomisd(XMMRegister dst, Address src);
23332333
void ucomisd(XMMRegister dst, XMMRegister src);
2334+
void vucomxsd(XMMRegister dst, Address src);
2335+
void vucomxsd(XMMRegister dst, XMMRegister src);
23342336

23352337
// Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
23362338
void ucomiss(XMMRegister dst, Address src);
23372339
void ucomiss(XMMRegister dst, XMMRegister src);
2340+
void vucomxss(XMMRegister dst, Address src);
2341+
void vucomxss(XMMRegister dst, XMMRegister src);
23382342

23392343
void xabort(int8_t imm8);
23402344

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp‎

Lines changed: 18 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2020, 2025, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2020, 2026, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -1049,17 +1049,28 @@ void C2_MacroAssembler::signum_fp(int opcode, XMMRegister dst, XMMRegister zero,
10491049

10501050
Label DONE_LABEL;
10511051

1052+
// Handle special cases +0.0/-0.0 and NaN, if argument is +0.0/-0.0 or NaN, return argument
1053+
// If AVX10.2 (or newer) floating point comparison instructions used, SF=1 for equal and unordered cases
1054+
// If other floating point comparison instructions used, ZF=1 for equal and unordered cases
10521055
if (opcode == Op_SignumF) {
1053-
ucomiss(dst, zero);
1054-
jcc(Assembler::equal, DONE_LABEL); // handle special case +0.0/-0.0, if argument is +0.0/-0.0, return argument
1055-
jcc(Assembler::parity, DONE_LABEL); // handle special case NaN, if argument NaN, return NaN
1056+
if (VM_Version::supports_avx10_2()) {
1057+
vucomxss(dst, zero);
1058+
jcc(Assembler::negative, DONE_LABEL);
1059+
} else {
1060+
ucomiss(dst, zero);
1061+
jcc(Assembler::equal, DONE_LABEL);
1062+
}
10561063
movflt(dst, one);
10571064
jcc(Assembler::above, DONE_LABEL);
10581065
xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), noreg);
10591066
} else if (opcode == Op_SignumD) {
1060-
ucomisd(dst, zero);
1061-
jcc(Assembler::equal, DONE_LABEL); // handle special case +0.0/-0.0, if argument is +0.0/-0.0, return argument
1062-
jcc(Assembler::parity, DONE_LABEL); // handle special case NaN, if argument NaN, return NaN
1067+
if (VM_Version::supports_avx10_2()) {
1068+
vucomxsd(dst, zero);
1069+
jcc(Assembler::negative, DONE_LABEL);
1070+
} else {
1071+
ucomisd(dst, zero);
1072+
jcc(Assembler::equal, DONE_LABEL);
1073+
}
10631074
movdbl(dst, one);
10641075
jcc(Assembler::above, DONE_LABEL);
10651076
xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), noreg);

‎src/hotspot/cpu/x86/macroAssembler_x86.cpp‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2668,6 +2668,17 @@ void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscra
26682668
}
26692669
}
26702670

2671+
void MacroAssembler::vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2672+
assert(rscratch != noreg || always_reachable(src), "missing");
2673+
2674+
if (reachable(src)) {
2675+
Assembler::vucomxsd(dst, as_Address(src));
2676+
} else {
2677+
lea(rscratch, src);
2678+
Assembler::vucomxsd(dst, Address(rscratch, 0));
2679+
}
2680+
}
2681+
26712682
void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
26722683
assert(rscratch != noreg || always_reachable(src), "missing");
26732684

@@ -2679,6 +2690,17 @@ void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscra
26792690
}
26802691
}
26812692

2693+
void MacroAssembler::vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2694+
assert(rscratch != noreg || always_reachable(src), "missing");
2695+
2696+
if (reachable(src)) {
2697+
Assembler::vucomxss(dst, as_Address(src));
2698+
} else {
2699+
lea(rscratch, src);
2700+
Assembler::vucomxss(dst, Address(rscratch, 0));
2701+
}
2702+
}
2703+
26822704
void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
26832705
assert(rscratch != noreg || always_reachable(src), "missing");
26842706

‎src/hotspot/cpu/x86/macroAssembler_x86.hpp‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -1314,10 +1314,18 @@ class MacroAssembler: public Assembler {
13141314
void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
13151315
void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
13161316

1317+
void vucomxss(XMMRegister dst, XMMRegister src) { Assembler::vucomxss(dst, src); }
1318+
void vucomxss(XMMRegister dst, Address src) { Assembler::vucomxss(dst, src); }
1319+
void vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1320+
13171321
void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
13181322
void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
13191323
void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
13201324

1325+
void vucomxsd(XMMRegister dst, XMMRegister src) { Assembler::vucomxsd(dst, src); }
1326+
void vucomxsd(XMMRegister dst, Address src) { Assembler::vucomxsd(dst, src); }
1327+
void vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1328+
13211329
// Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
13221330
void xorpd(XMMRegister dst, XMMRegister src);
13231331
void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }

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