Decode.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 05.02.2025 11:38:49
// Design Name: 
// Module Name: Decode
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Decode(
    input enable, //ready_fetch, ack_execute,
    input [31:0] instruction,
    input [9:0] instr_add,
    
    output ack_decode, ready_decode,
    output reg [0:5] type,
    output reg [9:0] address,
    output reg [3:0] alu_opcode,
    output reg [6:0] opcode,
    output reg [4:0] rs1, rs2, rdt,
    output reg [2:0] funct3,
    output reg [6:0] funct7,
    output reg [19:0] imm
    );
    
    wire r, i, s, b, u, j; 
    assign {r, i, s, b, u, j} = type;
    
    reg ready = 1;
    assign {ready_decode, ack_decode} = {ready, ready};
    
    reg [31:0] Instr;
    
    //wire enable = ready_fetch & ack_execute;
    
    always @ (posedge enable) begin
            #1 ready = 0;
            Instr = instruction;
            address = instr_add;
            #1;
            //Extracting the opcode from the instruction
            opcode = Instr[6:0];
            #1;
            //Obtaining the operand source and target addresses from the instruction
            rdt = Instr[11:7];
            rs1 = Instr[19:15];
            rs2 = Instr[24:20];
            #1;
            //Getting the functions from the instruction
            funct3 = Instr[14:12];
            funct7 = Instr[31:25];
            #1;
            //Deciding type of instruction based on opcode
            case(Instr[6:0])
                7'h33: type = 6'b100000;                //R
                7'h67, 7'h03, 7'h13: type = 6'b010000;  //I
                7'h23: type = 6'b001000;                //S
                7'h63: type = 6'b000100;                //B
                7'h37, 7'h17: type = 6'b000010;         //U
                7'h6f: type = 6'b000001;                //J
                default: type = 6'b000000;              //Invalid
            endcase
            #1;
            //Selecting ALU Opcode based on type of instruciton
            if(r | i) alu_opcode = {funct3, funct7[5]};
            else if(u) alu_opcode = 0;
            #1;
            //Deciding Immediate value based on type of instruction
            if(i) imm = funct7;
            else if(s) imm = {funct7, rs2};
            else if(b) imm = {Instr[31], Instr[7], funct7[5:0], Instr[11:8]};
            else if(u) imm = {funct7, rs2, rs1, funct3};
            else if(j) imm = {Instr[31], Instr[19:12], Instr[20], Instr[30:21]};
            
            ready = 1;
    end

endmodule