Fetch.v

`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 05.02.2025 11:40:59
// Design Name: 
// Module Name: Fetch
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Fetch(
    input enable, 
    input Reset, Branch,
    input [9:0] TargetAddress,
    input [31:0] plus32,
    
    output ready_fetch,
    output [31:0] Instruction, 
    output [9:0] Add
    );
    
    wire ack_decode = enable;
    wire [9:0] Address, Previous;
    wire [31:0] I;
    reg [9:0] JumpTo;
    wire ready;
        
    Prog_Count PC(
    .clk(ack_decode),
    .Reset(Reset),
    .Jump(Branch),
    .JumpTo(TargetAddress),
    .Address(Address));
            
    Prog_Mem IMEM(
    .Reset(Reset),
    .Address(Address),
    .Instruction(I),
    .plus32(plus32),
    .ready(ready)
    );
    
    assign ready_fetch = ready;
    
    assign Add  = Address;
    assign Instruction = I;
        
endmodule