clk: stm32: Update clock management for STM32MP13/21/25

During clock's registration, clock's name are used to establish parent -
child relation. Most of SCMI clocks are parent clocks.

Since commit fdb1bff ("clk: scmi: Postpone clock name resolution"),
all scmi clocks are named by default "scmi-%zu" until they are enabled,
it breaks clocks registration and boot process for STM32MP13/25
platforms.

Rework the STM32 core clock driver and STM32MP13/21/25 clock description
to use clock index instead of their real name.

Introduce struct clk_parent_data which allows to identify parent clock
either by index or by name. Name is only used for particular clocks
provided by IP which are clock provider as i2s/i2s_ckin, usb0/ck_usbo_48m,
and ltdc/ck_ker_ltdc.

STM32_GATE() and STM32_COMPOSITE_NOMUX macros are updated in order to
use parent clock index.

Change-Id: I7c7179df6ef3c9d4728c697bd0285e0fd908dcc3
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/543952
ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>

Author: Gabriel-Fernandz

drivers/clk/stm32/clk-stm32-core.c

@@ -12,6 +12,8 @@
 #include <log.h>
 #include <asm/io.h>
 #include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <dm/uclass-internal.h>
 #include <linux/clk-provider.h>
 #include "clk-stm32-core.h"
 
@@ -35,8 +37,8 @@ int stm32_rcc_init(struct udevice *dev,
 		return -ENOMEM;
 
 	priv->gate_cpt = cpt;
-
-	priv->data = clock_data;
+	priv->clock_data = clock_data;
+	priv->match_data = data;
 
 	for (i = 0; i < data->num_clocks; i++) {
 		const struct clock_config *cfg = &data->tab_clocks[i];
@@ -58,9 +60,50 @@ int stm32_rcc_init(struct udevice *dev,
 	return 0;
 }
 
-ulong clk_stm32_get_rate_by_name(const char *name)
+static int clk_stm32_resolve_clk_name(struct udevice *dev, int idx, const char **name)
+{
+	struct ofnode_phandle_args args;
+	struct udevice *clk_udevice;
+	struct udevice *child;
+	int ret;
+
+	ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, idx, &args);
+	if (ret) {
+		dev_err(dev, "%s: dev_read_phandle_with_args failed: err=%d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	ret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &clk_udevice);
+	if (ret)
+		return ret;
+
+	if (args.args_count) {
+		device_foreach_child(child, clk_udevice) {
+			struct clk *clkp;
+
+			clkp = dev_get_clk_ptr(child);
+			if (clk_get_id(clkp) == args.args[0])
+				break;
+
+			clk_udevice = child;
+		}
+		*name = child->name;
+	} else {
+		*name = clk_udevice->name;
+	}
+
+	return 0;
+}
+
+ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index)
 {
-	struct udevice *dev;
+	const char *name;
+	int ret;
+
+	ret = clk_stm32_resolve_clk_name(dev, index, &name);
+	if (ret)
+		return ret;
 
 	if (!uclass_get_device_by_name(UCLASS_CLK, name, &dev)) {
 		struct clk *clk = dev_get_clk_ptr(dev);
@@ -172,7 +215,7 @@ static int clk_stm32_gate_enable(struct clk *clk)
 	struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);
 	struct stm32mp_rcc_priv *priv = stm32_gate->priv;
 
-	clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,
+	clk_stm32_gate_set_state(priv->base, priv->clock_data, priv->gate_cpt,
 				 stm32_gate->gate_id, 1);
 
 	return 0;
@@ -183,7 +226,7 @@ static int clk_stm32_gate_disable(struct clk *clk)
 	struct clk_stm32_gate *stm32_gate = to_clk_stm32_gate(clk);
 	struct stm32mp_rcc_priv *priv = stm32_gate->priv;
 
-	clk_stm32_gate_set_state(priv->base, priv->data, priv->gate_cpt,
+	clk_stm32_gate_set_state(priv->base, priv->clock_data, priv->gate_cpt,
 				 stm32_gate->gate_id, 0);
 
 	return 0;
@@ -210,6 +253,7 @@ struct clk *clk_stm32_gate_register(struct udevice *dev,
 	struct stm32_clk_gate_cfg *clk_cfg = cfg->clock_cfg;
 	struct clk_stm32_gate *stm32_gate;
 	struct clk *clk;
+	const char *parent_name;
 	int ret;
 
 	stm32_gate = kzalloc(sizeof(*stm32_gate), GFP_KERNEL);
@@ -222,8 +266,17 @@ struct clk *clk_stm32_gate_register(struct udevice *dev,
 	clk = &stm32_gate->clk;
 	clk->flags = cfg->flags;
 
+	if (cfg->parent_data->name) {
+		parent_name = cfg->parent_data->name;
+	} else {
+		ret = clk_stm32_resolve_clk_name(dev, cfg->parent_data->index,
+						 &parent_name);
+		if (ret)
+			return ERR_PTR(ret);
+	}
+
 	ret = clk_register(clk, UBOOT_DM_CLK_STM32_GATE,
-			   cfg->name, cfg->parent_name);
+			   cfg->name, parent_name);
 	if (ret) {
 		kfree(stm32_gate);
 		return ERR_PTR(ret);
@@ -237,7 +290,7 @@ clk_stm32_register_composite(struct udevice *dev,
 			     const struct clock_config *cfg)
 {
 	struct stm32_clk_composite_cfg *composite = cfg->clock_cfg;
-	const char *const *parent_names;
+	const char **parent_names = NULL;
 	int num_parents;
 	struct clk *clk = ERR_PTR(-ENOMEM);
 	struct clk_mux *mux = NULL;
@@ -250,7 +303,8 @@ clk_stm32_register_composite(struct udevice *dev,
 	struct clk *div_clk = NULL;
 	const struct clk_ops *div_ops = NULL;
 	struct stm32mp_rcc_priv *priv = dev_get_priv(dev);
-	const struct clk_stm32_clock_data *data = priv->data;
+	const struct clk_stm32_clock_data *data = priv->clock_data;
+	int i, ret;
 
 	if  (composite->mux_id != NO_STM32_MUX) {
 		const struct stm32_mux_cfg *mux_cfg;
@@ -261,27 +315,50 @@ clk_stm32_register_composite(struct udevice *dev,
 
 		mux_cfg = &data->muxes[composite->mux_id];
 
+		parent_names = devm_kcalloc(dev, mux_cfg->num_parents,
+					    sizeof(char *), GFP_KERNEL);
+		if (!parent_names)
+			goto fail;
+
 		mux->reg = priv->base + mux_cfg->reg_off;
 		mux->shift = mux_cfg->shift;
 		mux->mask = BIT(mux_cfg->width) - 1;
 		mux->num_parents = mux_cfg->num_parents;
 		mux->flags = 0;
-		mux->parent_names = mux_cfg->parent_names;
 
+		for (i = 0; i < mux_cfg->num_parents; i++) {
+			if (mux_cfg->parent_data[i].name) {
+				parent_names[i] = mux_cfg->parent_data[i].name;
+			} else {
+				ret = clk_stm32_resolve_clk_name(dev,
+								 mux_cfg->parent_data[i].index,
+								 &parent_names[i]);
+				if (ret)
+					return ERR_CAST(clk);
+			}
+		}
+
+		mux->parent_names = (const char * const*)parent_names;
 		mux_clk = &mux->clk;
 		mux_ops = &clk_mux_ops;
-
-		parent_names = mux_cfg->parent_names;
 		num_parents = mux_cfg->num_parents;
 	} else {
-		parent_names = &cfg->parent_name;
+		parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
+		if (!parent_names)
+			goto fail;
+
+		ret = clk_stm32_resolve_clk_name(dev, cfg->parent_data->index,
+						 parent_names);
+		if (ret)
+			return ERR_CAST(clk);
+
 		num_parents = 1;
 	}
 
 	if  (composite->div_id != NO_STM32_DIV) {
 		const struct stm32_div_cfg *div_cfg;
 
-		div = kzalloc(sizeof(*div), GFP_KERNEL);
+		div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 		if (!div)
 			goto fail;
 
@@ -311,7 +388,7 @@ clk_stm32_register_composite(struct udevice *dev,
 	}
 
 	clk = clk_register_composite(NULL, cfg->name,
-				     parent_names, num_parents,
+				     (const char * const *)parent_names, num_parents,
 				     mux_clk, mux_ops,
 				     div_clk, div_ops,
 				     gate_clk, gate_ops,
@@ -322,6 +399,7 @@ clk_stm32_register_composite(struct udevice *dev,
 	return clk;
 
 fail:
+	kfree(parent_names);
 	kfree(gate);
 	kfree(div);
 	kfree(mux);

drivers/clk/stm32/clk-stm32-core.h

@@ -6,10 +6,20 @@
 
 struct stm32_clock_match_data;
 
+/**
+ * struct clk_parent_data - clk parent information
+ * @name: globally unique parent name
+ * @index: parent index local to provider registering clk
+ */
+struct clk_parent_data {
+	const char	*name;
+	int		index;
+};
+
 /**
  * struct stm32_mux_cfg - multiplexer configuration
  *
- * @parent_names:	array of string names for all possible parents
+ * @parent_data:	array of parent information for all possible parent
  * @num_parents:	number of possible parents
  * @reg_off:		register controlling multiplexer
  * @shift:		shift to multiplexer bit field
@@ -19,7 +29,7 @@ struct stm32_clock_match_data;
  *			index
  */
 struct stm32_mux_cfg {
-	const char * const *parent_names;
+	const struct clk_parent_data *parent_data;
 	u8 num_parents;
 	u32 reg_off;
 	u8 shift;
@@ -81,7 +91,7 @@ struct stm32_composite_cfg {
  *
  * @id:			binding id of the clock
  * @name:		clock name
- * @parent_name:	name of the clock parent
+ * @parent_data:	parent information
  * @flags:		framework-specific flags
  * @sec_id:		secure id (use to known if the clock is secured or not)
  * @clock_cfg:		specific clock data configuration
@@ -91,7 +101,7 @@ struct stm32_composite_cfg {
 struct clock_config {
 	unsigned long id;
 	const char *name;
-	const char *parent_name;
+	const struct clk_parent_data *parent_data;
 	unsigned long flags;
 	int sec_id;
 	void *clock_cfg;
@@ -129,6 +139,7 @@ struct stm32_clock_match_data {
 	const struct clk_stm32_clock_data *clock_data;
 	int (*check_security)(struct udevice *dev, void __iomem *base,
 			      const struct clock_config *cfg);
+	const char *(*get_clock_name)(u8 index);
 };
 
 /**
@@ -143,7 +154,8 @@ struct stm32_clock_match_data {
 struct stm32mp_rcc_priv {
 	void __iomem *base;
 	u8 *gate_cpt;
-	const struct clk_stm32_clock_data *data;
+	const struct clk_stm32_clock_data *clock_data;
+	const struct stm32_clock_match_data *match_data;
 };
 
 int stm32_rcc_init(struct udevice *dev,
@@ -223,12 +235,14 @@ struct stm32_clk_gate_cfg {
 
 #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \
 { \
-	.id		= _id, \
-	.sec_id		= _sec_id, \
-	.name		= _name, \
-	.parent_name	= _parent, \
-	.flags		= _flags, \
-	.clock_cfg	= &(struct stm32_clk_gate_cfg) { \
+	.id			= _id, \
+	.sec_id			= _sec_id, \
+	.name			= _name, \
+	.parent_data		= &(struct clk_parent_data) { \
+		.index		= _parent, \
+	}, \
+	.flags			= _flags, \
+	.clock_cfg		= &(struct stm32_clk_gate_cfg) { \
 		.gate_id	= _gate_id, \
 	}, \
 	.setup		= clk_stm32_gate_register, \
@@ -260,7 +274,9 @@ struct stm32_clk_composite_cfg {
 { \
 	.id		= _id, \
 	.name		= _name, \
-	.parent_name	= _parent, \
+	.parent_data		= &(struct clk_parent_data) { \
+		.index		= _parent, \
+	}, \
 	.sec_id		= _sec_id, \
 	.flags		= _flags, \
 	.clock_cfg	= &(struct stm32_clk_composite_cfg) { \
@@ -273,4 +289,4 @@ struct stm32_clk_composite_cfg {
 
 extern const struct clk_ops stm32_clk_ops;
 
-ulong clk_stm32_get_rate_by_name(const char *name);
+ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index);