armv8: Fix declaration of bit 20 for sctrl_el1

ARM DDI 0487 L.a reports that, in AArch64, bit 20 of sctrl_el1 is
RES1 only when FEAT_CSV2_2 and FEAT_CSV2_1p2 are not implemented.
Otherwise, the bit 20 is TSCXT that, when set, disables EL0 access
to SCXTNUM_EL0.

In AArch32, the bits sctrl_el1[31:0] are mapped to sctrl[31:0] and
the bit 20 gets mapper to UWXN which, when set, causes all memory
regions that are writable at PL0 to be treated as XN for accesses
from software executing at PL1.

The current code considers this bit as always RES1, thus sets it
in the macro 'armv8_switch_to_el1_m'.

Move bit 20 outside the macro SCTLR_EL1_RES1 and list it as one of
the bits of sctrl_el1, reporting its behavior for both AArch64 and
AArch32.

Please note that other bits in sctrl_el1 have been assigned to new
functionalities in ARM DDI 0487 L.a, but not addressed here.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I12e0b10e059c172dc25b414f41c23370c436d8ee
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/565213
ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
Domain-Review: Amelie DELAUNAY <amelie.delaunay@foss.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Reviewed-by: Amelie DELAUNAY <amelie.delaunay@foss.st.com>

Author: AntonioBorneo

arch/arm/include/asm/macro.h

@@ -265,7 +265,7 @@ lr	.req	x30
 
 	/* SCTLR_EL1 initialization
 	 *
-	 * setting RES1 bits (29,28,23,22,20,11) to 1
+	 * setting RES1 bits (29,28,23,22,11) to 1
 	 * and RES0 bits (31,30,27,21,17,13,10,6) +
 	 * UCI,EE,EOE,WXN,nTWE,nTWI,UCT,DZE,I,UMA,SED,ITD,
 	 * CP15BEN,SA0,SA,C,A,M to 0

arch/arm/include/asm/system.h

@@ -109,10 +109,13 @@
 /*
  * SCTLR_EL1 bits definitions
  */
-#define SCTLR_EL1_RES1		(3 << 28 | 3 << 22 | 1 << 20 |\
+#define SCTLR_EL1_RES1		(3 << 28 | 3 << 22 |\
 				 1 << 11) /* Reserved, RES1                   */
 #define SCTLR_EL1_UCI_DIS	(0 << 26) /* Cache instruction disabled       */
 #define SCTLR_EL1_EE_LE		(0 << 25) /* Exception Little-endian          */
+#define SCTLR_EL1_TSCXT_UWXN	(0 << 20) /* Trap EL0 access to SCXTNUM_EL0 or
+					     Unprivileged write permission is
+					     not XN */
 #define SCTLR_EL1_WXN_DIS	(0 << 19) /* Write permission is not XN       */
 #define SCTLR_EL1_NTWE_DIS	(0 << 18) /* WFE instruction disabled         */
 #define SCTLR_EL1_NTWI_DIS	(0 << 16) /* WFI instruction disabled         */