video: stm32: ltdc: Set configuration register masks to 12 bits

The display configuration registers vary between LTDC IP versions.
The registers controlling height settings are 11 or 12-bit based.
Therefore, the masks must be updated depending on the LTDC IP version.

Change-Id: Idcffa08941ff681917273e28a5937e5c71765745
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/444327
ACI: CITOOLS <MDG-smet-aci-reviews@list.st.com>
ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>

Author: Yannick Fertre

drivers/video/stm32/stm32_ltdc.c

@@ -44,6 +44,7 @@ struct stm32_ltdc_priv {
 	u32 bg_col_argb;
 	const u32 *layer_regs;
 	const u32 *pix_fmt_hw;
+	const u32 *conf_regs;
 	u32 crop_x, crop_y, crop_w, crop_h;
 	u32 alpha;
 	u32 hw_version;
@@ -154,6 +155,28 @@ static const u32 layer_regs_a2[] = {
 	0x178	/* L1 Flexible Pixel Format 1 */
 };
 
+static const u32 ltdc_conf_regs_a0[] = {
+	GENMASK(10, 0),		/* Vertical Synchronization Height */
+	GENMASK(27, 16),	/* Horizontal Synchronization Width */
+	GENMASK(10, 0),		/* Accumulated Vertical Back Porch */
+	GENMASK(27, 16),	/* Accumulated Horizontal Back Porch */
+	GENMASK(10, 0),		/* Accumulated Active Height */
+	GENMASK(27, 16),	/* Accumulated Active Width */
+	GENMASK(10, 0),		/* TOTAL Height */
+	GENMASK(27, 16)		/* TOTAL Width */
+};
+
+static const u32 ltdc_conf_regs_a1[] = {
+	GENMASK(11, 0),		/* Vertical Synchronization Height */
+	GENMASK(27, 16),	/* Horizontal Synchronization Width */
+	GENMASK(11, 0),		/* Accumulated Vertical Back Porch */
+	GENMASK(27, 16),	/* Accumulated Horizontal Back Porch */
+	GENMASK(11, 0),		/* Accumulated Active Height */
+	GENMASK(27, 16),	/* Accumulated Active Width */
+	GENMASK(11, 0),		/* TOTAL Height */
+	GENMASK(27, 16)		/* TOTAL Width */
+};
+
 /* LTDC main registers */
 #define LTDC_IDR	0x00	/* IDentification */
 #define LTDC_LCR	0x04	/* Layer Count */
@@ -211,17 +234,14 @@ static const u32 layer_regs_a2[] = {
 #define LTDC_L1FPF1R	(priv->layer_regs[30])	/* L1 Flexible Pixel Format 1 */
 
 /* Bit definitions */
-#define SSCR_VSH	GENMASK(10, 0)	/* Vertical Synchronization Height */
-#define SSCR_HSW	GENMASK(27, 16)	/* Horizontal Synchronization Width */
-
-#define BPCR_AVBP	GENMASK(10, 0)	/* Accumulated Vertical Back Porch */
-#define BPCR_AHBP	GENMASK(27, 16)	/* Accumulated Horizontal Back Porch */
-
-#define AWCR_AAH	GENMASK(10, 0)	/* Accumulated Active Height */
-#define AWCR_AAW	GENMASK(27, 16)	/* Accumulated Active Width */
-
-#define TWCR_TOTALH	GENMASK(10, 0)	/* TOTAL Height */
-#define TWCR_TOTALW	GENMASK(27, 16)	/* TOTAL Width */
+#define SSCR_VSH	(priv->conf_regs[0])	/* Vertical Synchronization Height */
+#define SSCR_HSW	(priv->conf_regs[1])	/* Horizontal Synchronization Width */
+#define BPCR_AVBP	(priv->conf_regs[2])	/* Accumulated Vertical Back Porch */
+#define BPCR_AHBP	(priv->conf_regs[3])	/* Accumulated Horizontal Back Porch */
+#define AWCR_AAH	(priv->conf_regs[4])	/* Accumulated Active Height */
+#define AWCR_AAW	(priv->conf_regs[5])	/* Accumulated Active Width */
+#define TWCR_TOTALH	(priv->conf_regs[6])	/* TOTAL Height */
+#define TWCR_TOTALW	(priv->conf_regs[7])	/* TOTAL Width */
 
 #define GCR_LTDCEN	BIT(0)		/* LTDC ENable */
 #define GCR_ROTEN	BIT(2)		/* ROTation ENable */
@@ -903,18 +923,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 	switch (priv->hw_version) {
 	case HWVER_10200:
+		priv->layer_regs = layer_regs_a0;
+		priv->pix_fmt_hw = pix_fmt_a0;
+		priv->conf_regs = ltdc_conf_regs_a0;
+		break;
 	case HWVER_10300:
 		priv->layer_regs = layer_regs_a0;
 		priv->pix_fmt_hw = pix_fmt_a0;
+		priv->conf_regs = ltdc_conf_regs_a1;
 		break;
 	case HWVER_20101:
 		priv->layer_regs = layer_regs_a1;
 		priv->pix_fmt_hw = pix_fmt_a1;
+		priv->conf_regs = ltdc_conf_regs_a1;
 		break;
 	case HWVER_40100:
 	case HWVER_40101:
 		priv->layer_regs = layer_regs_a2;
 		priv->pix_fmt_hw = pix_fmt_a2;
+		priv->conf_regs = ltdc_conf_regs_a1;
 		break;
 	default:
 		return -ENODEV;