spi: stm32_spi: add stm32mp25 / limited-featured support

On STM32MP25 some SPI instances are limited-featured with
smaller maximum transfer size.
In order to support this, add a st,stm32mp25-spi new compatible
and check a STM32MP25 specific register field which indicate
if the instance has full or limited feature-set.

Change-Id: I986c9f1bb0fbde9067627aee8b0cc29e1c854da9
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/523210
Domain-Review: Amelie DELAUNAY <amelie.delaunay@foss.st.com>
Tested-by: Alain VOLMAT <alain.volmat@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
ACI: CITOOLS <MDG-smet-aci-reviews@list.st.com>
ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Alain VOLMAT <alain.volmat@st.com>

Author: Alain Volmat

drivers/spi/stm32_spi.c

@@ -35,6 +35,8 @@
 #define STM32_SPI_RXDR		0x30
 #define STM32_SPI_I2SCFGR	0x50
 
+#define STM32MP25_SPI_HWCFGR1	0x3F0
+
 /* STM32_SPI_CR1 bit fields */
 #define SPI_CR1_SPE		BIT(0)
 #define SPI_CR1_MASRX		BIT(8)
@@ -45,6 +47,7 @@
 
 /* STM32_SPI_CR2 bit fields */
 #define SPI_CR2_TSIZE		GENMASK(15, 0)
+#define SPI_CR2_TSIZE_LIMITED	GENMASK(9, 0)
 
 /* STM32_SPI_CFG1 bit fields */
 #define SPI_CFG1_DSIZE		GENMASK(4, 0)
@@ -83,6 +86,11 @@
 /* STM32_SPI_I2SCFGR bit fields */
 #define SPI_I2SCFGR_I2SMOD	BIT(0)
 
+/* STM32MP25_SPI_HWCFGR1 */
+#define STM32MP25_SPI_HWCFGR1_FULLCFG		GENMASK(27, 24)
+#define STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED	0x0
+#define STM32MP25_SPI_HWCFGR1_FULLCFG_FULL	0x1
+
 #define MAX_CS_COUNT	4
 
 /* SPI Master Baud Rate min/max divisor */
@@ -107,6 +115,7 @@ struct stm32_spi_plat {
 struct stm32_spi_priv {
 	ulong bus_clk_rate;
 	unsigned int fifo_size;
+	unsigned int max_xferlen; /* maximum transfer length */
 	unsigned int cur_bpw;
 	unsigned int cur_hz;
 	unsigned int cur_xferlen; /* current transfer length in bytes */
@@ -397,7 +406,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
 
 	xferlen = bitlen / 8;
 
-	if (xferlen <= SPI_CR2_TSIZE)
+	if (xferlen <= priv->max_xferlen)
 		writel(xferlen, base + STM32_SPI_CR2);
 	else
 		return -EMSGSIZE;
@@ -508,6 +517,31 @@ static int stm32_spi_get_fifo_size(struct udevice *dev)
 	return count;
 }
 
+static unsigned int stm32_spi_get_max_xferlen(struct udevice *dev)
+{
+	struct stm32_spi_plat *plat = dev_get_plat(dev);
+	void __iomem *base = plat->base;
+	unsigned int max_xfer_len = SPI_CR2_TSIZE;
+
+	/*
+	 * On STM32MP2x, the maximum size depends on the capabilities
+	 * of the instance, which can be checked via FULLCFG of register
+	 * SPI_HWCFGR1
+	 */
+	if (device_is_compatible(dev, "st,stm32mp25-spi")) {
+		unsigned int hwcfgr1 = readl(base + STM32MP25_SPI_HWCFGR1);
+
+		if (FIELD_GET(STM32MP25_SPI_HWCFGR1_FULLCFG, hwcfgr1) ==
+		    STM32MP25_SPI_HWCFGR1_FULLCFG_LIMITED) {
+			max_xfer_len = SPI_CR2_TSIZE_LIMITED;
+			dev_dbg(dev, "limited-featured, max xfer len = %ld\n",
+				SPI_CR2_TSIZE_LIMITED);
+		}
+	}
+
+	return max_xfer_len;
+}
+
 static int stm32_spi_of_to_plat(struct udevice *dev)
 {
 	struct stm32_spi_plat *plat = dev_get_plat(dev);
@@ -571,6 +605,7 @@ static int stm32_spi_probe(struct udevice *dev)
 	reset_deassert(&plat->rst_ctl);
 
 	priv->fifo_size = stm32_spi_get_fifo_size(dev);
+	priv->max_xferlen = stm32_spi_get_max_xferlen(dev);
 	priv->cur_mode = SPI_FULL_DUPLEX;
 	priv->cur_xferlen = 0;
 	priv->cur_bpw = SPI_DEFAULT_WORDLEN;
@@ -648,6 +683,7 @@ static const struct dm_spi_ops stm32_spi_ops = {
 
 static const struct udevice_id stm32_spi_ids[] = {
 	{ .compatible = "st,stm32h7-spi", },
+	{ .compatible = "st,stm32mp25-spi", },
 	{ }
 };