board: stm32pm2: support st,eth-clk-sel property

When this property is set, internal RCC clock is used for the RGMII
125MHz clock selection.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Change-Id: Ibb48a3403696f17c1331ab4c119e78aa07b1ceb1
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/u-boot/+/460024
Reviewed-by: Christophe ROULLIER <christophe.roullier@foss.st.com>
ACI: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Gatien CHEVALLIER <gatien.chevallier@st.com>
ACI: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Tested-by: Gatien CHEVALLIER <gatien.chevallier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@foss.st.com>
Tested-by: Christophe ROULLIER <christophe.roullier@foss.st.com>
Domain-Review: Christophe ROULLIER <christophe.roullier@foss.st.com>

Author: GseoC

board/st/stm32mp2/stm32mp2.c

@@ -480,7 +480,8 @@ int board_interface_eth_init(struct udevice *dev,
 	bool ext_phyclk;
 
 	/* Ethernet PHY have no cristal or need to be clock by RCC */
-	ext_phyclk = dev_read_bool(dev, "st,ext-phyclk");
+	ext_phyclk = dev_read_bool(dev, "st,ext-phyclk") || dev_read_bool(dev, "st,eth-clk-sel") ||
+		     dev_read_bool(dev, "st,eth-ref-clk-sel");
 
 	regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon");