Skip to content

Commit 1ecd2c9

Browse files
Samir-RashidSamir-Rashid
committed
test: run translation from RISCV to ARM enums
1 parent 7db7eec commit 1ecd2c9

5 files changed

Lines changed: 222 additions & 97 deletions

File tree

‎src/instruction.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -207,7 +207,7 @@ pub enum RiscVVal {
207207
Immediate(i32),
208208
/// This is for arguments to opcodes which have an offset
209209
Offset {
210-
register: Box<RiscVRegister>,
210+
register: RiscVRegister,
211211
offset: i32,
212212
},
213213
}

‎src/translate.rs‎

Lines changed: 58 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -99,19 +99,73 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
9999
}
100100

101101
fn map_register(riscv_reg: RiscVRegister) -> ArmRegister {
102-
todo!()
102+
match riscv_reg {
103+
RiscVRegister::X0 => todo!("Arm doesn't have a zero register"),
104+
// RiscVRegister::RA => ArmRegister::Lr,
105+
// RiscVRegister::SP => ArmRegister::Sp,
106+
// RiscVRegister::GP => ArmRegister::,
107+
// RiscVRegister::TP => ArmRegister::,
108+
// RiscVRegister::T0 => ArmRegister::,
109+
// RiscVRegister::T1 => ArmRegister::,
110+
// RiscVRegister::T2 => ArmRegister::,
111+
// RiscVRegister::S0FP => ArmRegister::,
112+
// RiscVRegister::S1 => ArmRegister::,
113+
// RiscVRegister::A0 => ArmRegister::,
114+
// RiscVRegister::A1 => ArmRegister::,
115+
// RiscVRegister::A2 => ArmRegister::,
116+
// RiscVRegister::A3 => ArmRegister::,
117+
// RiscVRegister::A4 => ArmRegister::,
118+
// RiscVRegister::A5 => ArmRegister::,
119+
// RiscVRegister::A6 => ArmRegister::,
120+
// RiscVRegister::A7 => ArmRegister::,
121+
// RiscVRegister::S2 => ArmRegister::,
122+
// RiscVRegister::S3 => ArmRegister::,
123+
// RiscVRegister::S4 => ArmRegister::,
124+
// RiscVRegister::S5 => ArmRegister::,
125+
// RiscVRegister::S6 => ArmRegister::,
126+
// RiscVRegister::S7 => ArmRegister::,
127+
// RiscVRegister::S8 => ArmRegister::,
128+
// RiscVRegister::S9 => ArmRegister::,
129+
// RiscVRegister::S10 => ArmRegister::,
130+
// RiscVRegister::S11 => ArmRegister::,
131+
// RiscVRegister::T3 => ArmRegister::,
132+
// RiscVRegister::T4 => ArmRegister::,
133+
// RiscVRegister::T5 => ArmRegister::,
134+
// RiscVRegister::T6 => ArmRegister::,
135+
// FIXME: do real implementation
136+
_ => ArmRegister {
137+
width: ArmWidth::Double,
138+
name: ArmRegisterName::Sp,
139+
},
140+
}
103141
}
104142

105143
fn map_register_name(riscv_reg: RiscVRegister) -> ArmRegisterName {
106-
todo!()
144+
// todo!()
145+
// FIXME: do real implementation
146+
ArmRegisterName::A1
107147
}
108148

109149
fn map_val(riscv_val: RiscVVal) -> ArmVal {
110-
todo!()
150+
match riscv_val {
151+
RiscVVal::RiscVRegister(riscv_reg) => ArmVal::Reg(map_register(riscv_reg)),
152+
RiscVVal::Immediate(imm) => ArmVal::Imm(imm),
153+
RiscVVal::Offset { register, offset } => ArmVal::RegOffset(map_register(register), offset),
154+
}
111155
}
112156

113157
fn map_width(riscv_width: RiscVWidth) -> ArmWidth {
114-
todo!()
158+
// todo!()
159+
// FIXME: do real implementation
160+
ArmWidth::Double
161+
}
162+
163+
// Translate every instruction 1:1
164+
pub fn translate_instrs(riscv_instrs: Vec<RiscVInstruction>) -> Vec<ArmInstruction> {
165+
riscv_instrs
166+
.into_iter()
167+
.map(|instr| translate(instr))
168+
.collect::<Vec<ArmInstruction>>()
115169
}
116170

117171
/// Runs binary translation

‎tests/binaries/add.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ int main(void) {
2222
// sext.w a5,a5
2323
// mv a0,a5
2424
// ld ra,24(sp)
25-
// ld ß s0,16(sp)
25+
// ld s0,16(sp)
2626
// addi sp,sp,32
2727
// jr ra
2828

@@ -38,4 +38,3 @@ int main(void) {
3838
// add w0, w1, w0
3939
// add sp, sp, 16
4040
// ret
41-

‎tests/test_parse_asm.rs‎

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,48 @@
1-
#[cfg(test)]
2-
mod tests {
3-
use binary_room::instruction::parse_asm;
1+
// #[cfg(test)]
2+
// mod tests {
3+
// use binary_room::instruction::parse_asm;
44

5-
#[test]
6-
fn test_parse_asm() {
7-
let asm = "
8-
addi sp,sp,-32
9-
sd ra,24(sp)
10-
ld s0,16(sp)
11-
addi s0,sp,32
12-
li a5,3
13-
sw a5,-20(s0)
14-
li a5,4
15-
sw a5,-24(s0)
16-
lw a5,-20(s0)
17-
mv a4,a5
18-
lw a5,-24(s0)
19-
addw a5,a4,a5
20-
sext.w a5,a5
21-
mv a0,a5
22-
ld ra,24(sp)
23-
ld s0,16(sp)
24-
addi sp,sp,32
25-
jr ra
26-
";
27-
let instructions = parse_asm(asm);
28-
assert_eq!(instructions.len(), 17);
29-
assert_eq!(instructions[0], RiscVInstruction::Addi);
30-
assert_eq!(instructions[1], RiscVInstruction::Sd);
31-
assert_eq!(instructions[2], RiscVInstruction::Ld);
32-
assert_eq!(instructions[3], RiscVInstruction::Addi);
33-
assert_eq!(instructions[4], RiscVInstruction::Li);
34-
assert_eq!(instructions[5], RiscVInstruction::Sw);
35-
assert_eq!(instructions[6], RiscVInstruction::Li);
36-
assert_eq!(instructions[7], RiscVInstruction::Sw);
37-
assert_eq!(instructions[8], RiscVInstruction::Lw);
38-
assert_eq!(instructions[9], RiscVInstruction::Mv);
39-
assert_eq!(instructions[10], RiscVInstruction::Lw);
40-
assert_eq!(instructions[11], RiscVInstruction::Addw);
41-
assert_eq!(instructions[12], RiscVInstruction::SextW);
42-
assert_eq!(instructions[13], RiscVInstruction::Mv);
43-
assert_eq!(instructions[14], RiscVInstruction::Ld);
44-
assert_eq!(instructions[15], RiscVInstruction::Ld);
45-
assert_eq!(instructions[16], RiscVInstruction::Addi);
46-
assert_eq!(instructions[17], RiscVInstruction::Jr);
47-
}
48-
}
5+
// #[test]
6+
// fn test_parse_asm() {
7+
// let asm = "
8+
// addi sp,sp,-32
9+
// sd ra,24(sp)
10+
// ld s0,16(sp)
11+
// addi s0,sp,32
12+
// li a5,3
13+
// sw a5,-20(s0)
14+
// li a5,4
15+
// sw a5,-24(s0)
16+
// lw a5,-20(s0)
17+
// mv a4,a5
18+
// lw a5,-24(s0)
19+
// addw a5,a4,a5
20+
// sext.w a5,a5
21+
// mv a0,a5
22+
// ld ra,24(sp)
23+
// ld s0,16(sp)
24+
// addi sp,sp,32
25+
// jr ra
26+
// ";
27+
// let instructions = parse_asm(asm);
28+
// assert_eq!(instructions.len(), 17);
29+
// assert_eq!(instructions[0], RiscVInstruction::Addi);
30+
// assert_eq!(instructions[1], RiscVInstruction::Sd);
31+
// assert_eq!(instructions[2], RiscVInstruction::Ld);
32+
// assert_eq!(instructions[3], RiscVInstruction::Addi);
33+
// assert_eq!(instructions[4], RiscVInstruction::Li);
34+
// assert_eq!(instructions[5], RiscVInstruction::Sw);
35+
// assert_eq!(instructions[6], RiscVInstruction::Li);
36+
// assert_eq!(instructions[7], RiscVInstruction::Sw);
37+
// assert_eq!(instructions[8], RiscVInstruction::Lw);
38+
// assert_eq!(instructions[9], RiscVInstruction::Mv);
39+
// assert_eq!(instructions[10], RiscVInstruction::Lw);
40+
// assert_eq!(instructions[11], RiscVInstruction::Addw);
41+
// assert_eq!(instructions[12], RiscVInstruction::SextW);
42+
// assert_eq!(instructions[13], RiscVInstruction::Mv);
43+
// assert_eq!(instructions[14], RiscVInstruction::Ld);
44+
// assert_eq!(instructions[15], RiscVInstruction::Ld);
45+
// assert_eq!(instructions[16], RiscVInstruction::Addi);
46+
// assert_eq!(instructions[17], RiscVInstruction::Jr);
47+
// }
48+
// }

‎tests/test_translation.rs‎

Lines changed: 115 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,50 +1,122 @@
11
#[cfg(test)]
22
mod tests {
3-
use binary_room::translate::binary_translate;
3+
use binary_room::instruction::*;
4+
use binary_room::translate::*;
45

56
#[test]
67
fn test_binary_translate() {
7-
let riscv_asm = "
8-
addi sp,sp,-32
9-
sd ra,24(sp)
10-
ld s0,16(sp)
11-
addi s0,sp,32
12-
li a5,3
13-
sw a5,-20(s0)
14-
li a5,4
15-
sw a5,-24(s0)
16-
lw a5,-20(s0)
17-
mv a4,a5
18-
lw a5,-24(s0)
19-
addw a5,a4,a5
20-
sext.w a5,a5
21-
mv a0,a5
22-
ld ra,24(sp)
23-
ld s0,16(sp)
24-
addi sp,sp,32
25-
jr ra
26-
";
27-
let translated_asm = binary_translate(riscv_asm);
28-
let expected_output = "
29-
Addi
30-
Sd
31-
Ld
32-
Addi
33-
Li
34-
Sw
35-
Li
36-
Sw
37-
Lw
38-
Mv
39-
Lw
40-
Addw
41-
SextW
42-
Mv
43-
Ld
44-
Ld
45-
Addi
46-
Jr
47-
";
48-
assert_eq!(translated_asm, expected_output);
8+
let riscv_asm: Vec<RiscVInstruction> = vec![
9+
RiscVInstruction::Addi {
10+
dest: RiscVRegister::SP,
11+
src: RiscVRegister::SP,
12+
imm: -32,
13+
},
14+
RiscVInstruction::S {
15+
width: RiscVWidth::Double,
16+
src: RiscVRegister::RA,
17+
dest: RiscVVal::Offset {
18+
register: RiscVRegister::SP,
19+
offset: 24,
20+
},
21+
},
22+
RiscVInstruction::S {
23+
width: RiscVWidth::Double,
24+
src: RiscVRegister::S0FP,
25+
dest: RiscVVal::Offset {
26+
register: RiscVRegister::SP,
27+
offset: 16,
28+
},
29+
},
30+
RiscVInstruction::Addi {
31+
dest: RiscVRegister::S0FP,
32+
src: RiscVRegister::SP,
33+
imm: 32,
34+
},
35+
RiscVInstruction::Li {
36+
dest: RiscVRegister::A5,
37+
imm: 3,
38+
},
39+
RiscVInstruction::S {
40+
width: RiscVWidth::Word,
41+
src: RiscVRegister::A5,
42+
dest: RiscVVal::Offset {
43+
register: RiscVRegister::S0FP,
44+
offset: -20,
45+
},
46+
},
47+
RiscVInstruction::Li {
48+
dest: RiscVRegister::A5,
49+
imm: 4,
50+
},
51+
RiscVInstruction::S {
52+
width: RiscVWidth::Word,
53+
src: RiscVRegister::A5,
54+
dest: RiscVVal::Offset {
55+
register: RiscVRegister::S0FP,
56+
offset: -24,
57+
},
58+
},
59+
RiscVInstruction::L {
60+
width: RiscVWidth::Word,
61+
dest: RiscVRegister::A5,
62+
src: RiscVVal::Offset {
63+
register: RiscVRegister::S0FP,
64+
offset: -20,
65+
},
66+
},
67+
RiscVInstruction::Mv {
68+
dest: RiscVRegister::A4,
69+
src: RiscVRegister::A5,
70+
},
71+
RiscVInstruction::L {
72+
width: RiscVWidth::Word,
73+
dest: RiscVRegister::A5,
74+
src: RiscVVal::Offset {
75+
register: RiscVRegister::S0FP,
76+
offset: -24,
77+
},
78+
},
79+
RiscVInstruction::Add {
80+
width: RiscVWidth::Word,
81+
dest: RiscVRegister::A5,
82+
arg1: RiscVRegister::A4,
83+
arg2: RiscVRegister::A5,
84+
},
85+
RiscVInstruction::SextW {
86+
dest: RiscVRegister::A5,
87+
src: RiscVRegister::A5,
88+
},
89+
RiscVInstruction::Mv {
90+
dest: RiscVRegister::A0,
91+
src: RiscVRegister::A5,
92+
},
93+
RiscVInstruction::L {
94+
width: RiscVWidth::Double,
95+
dest: RiscVRegister::RA,
96+
src: RiscVVal::Offset {
97+
register: RiscVRegister::SP,
98+
offset: 24,
99+
},
100+
},
101+
RiscVInstruction::L {
102+
width: RiscVWidth::Double,
103+
dest: RiscVRegister::S0FP,
104+
src: RiscVVal::Offset {
105+
register: RiscVRegister::SP,
106+
offset: 16,
107+
},
108+
},
109+
RiscVInstruction::Addi {
110+
dest: RiscVRegister::SP,
111+
src: RiscVRegister::SP,
112+
imm: 32,
113+
},
114+
RiscVInstruction::Jr {
115+
target: RiscVRegister::RA,
116+
},
117+
];
118+
119+
println!("{:?}", translate_instrs(riscv_asm))
120+
// assert_eq!(translated_asm, expected_output);
49121
}
50122
}

0 commit comments

Comments
 (0)