@@ -20,33 +20,33 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
2020 let width = RiscVWidth :: Word ;
2121 if imm >= 0 {
2222 ArmInstruction :: Add {
23- dest : map_register ( dest, width) ,
24- arg1 : map_register ( src, width) ,
23+ dest : map_register ( dest, & width) ,
24+ arg1 : map_register ( src, & width) ,
2525 arg2 : ArmVal :: Imm ( imm) ,
2626 }
2727 } else {
2828 ArmInstruction :: Sub {
29- dest : map_register ( dest, width) ,
30- arg1 : map_register ( src, width) ,
29+ dest : map_register ( dest, & width) ,
30+ arg1 : map_register ( src, & width) ,
3131 arg2 : ArmVal :: Imm ( imm) ,
3232 }
3333 }
3434 }
3535 RiscVInstruction :: S { width, src, dest } => ArmInstruction :: Str {
36- width : map_width ( width) ,
37- src : map_register ( src, width) ,
38- dest : map_val ( dest, width) ,
36+ width : map_width ( & width) ,
37+ src : map_register ( src, & width) ,
38+ dest : map_val ( dest, & width) ,
3939 } ,
4040 RiscVInstruction :: L { width, dest, src } => ArmInstruction :: Ldr {
41- width : map_width ( width) ,
42- dest : map_register ( dest, width) ,
43- src : map_val ( src, width) ,
41+ width : map_width ( & width) ,
42+ dest : map_register ( dest, & width) ,
43+ src : map_val ( src, & width) ,
4444 } ,
4545 RiscVInstruction :: Mv { dest, src } => {
4646 let width = RiscVWidth :: Double ;
4747 ArmInstruction :: Add {
48- dest : map_register ( dest, width) ,
49- arg1 : map_register ( src, width) ,
48+ dest : map_register ( dest, & width) ,
49+ arg1 : map_register ( src, & width) ,
5050 arg2 : ArmVal :: Imm ( 0 ) ,
5151 }
5252 } ,
@@ -91,7 +91,7 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
9191 }
9292
9393 ArmInstruction :: Add {
94- dest : map_register ( dest, RiscVWidth :: Double ) ,
94+ dest : map_register ( dest, & RiscVWidth :: Double ) ,
9595 arg1 : ArmRegister {
9696 width : ArmWidth :: Double ,
9797 name : ArmRegisterName :: Zero ,
@@ -102,7 +102,7 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
102102 }
103103}
104104
105- fn map_register ( riscv_reg : RiscVRegister , riscv_width : RiscVWidth ) -> ArmRegister {
105+ fn map_register ( riscv_reg : RiscVRegister , riscv_width : & RiscVWidth ) -> ArmRegister {
106106 ArmRegister {
107107 width : map_width ( riscv_width) ,
108108 name : map_register_name ( riscv_reg)
@@ -115,15 +115,15 @@ fn map_register_name(riscv_reg: RiscVRegister) -> ArmRegisterName {
115115 ArmRegisterName :: A1
116116}
117117
118- fn map_val ( riscv_val : RiscVVal , riscv_width : RiscVWidth ) -> ArmVal {
118+ fn map_val ( riscv_val : RiscVVal , riscv_width : & RiscVWidth ) -> ArmVal {
119119 match riscv_val {
120120 RiscVVal :: RiscVRegister ( riscv_reg) => ArmVal :: Reg ( map_register ( riscv_reg, riscv_width) ) ,
121121 RiscVVal :: Immediate ( imm) => ArmVal :: Imm ( imm) ,
122122 RiscVVal :: Offset { register, offset } => ArmVal :: RegOffset ( map_register ( register, riscv_width) , offset) ,
123123 }
124124}
125125
126- fn map_width ( riscv_width : RiscVWidth ) -> ArmWidth {
126+ fn map_width ( riscv_width : & RiscVWidth ) -> ArmWidth {
127127 // todo!()
128128 // FIXME: do real implementation
129129 ArmWidth :: Double
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