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| 1 | +#[cfg(test)] |
| 2 | +mod tests { |
| 3 | + use binary_room::instruction::*; |
| 4 | + use binary_room::translate::*; |
| 5 | + use binary_room::utils; |
| 6 | + use binary_room::utils::translate_to_file; |
| 7 | + use binary_room::utils::START; |
| 8 | + |
| 9 | +const buf: &str = r#" |
| 10 | +.buf: |
| 11 | + .string "hello world" |
| 12 | +"#; |
| 13 | + |
| 14 | + #[test] |
| 15 | + fn test_print_translate() { |
| 16 | + let riscv_asm: Vec<RiscVInstruction> = vec![ |
| 17 | + // RiscVInstruction::Verbatim { text: buf.to_string() }, |
| 18 | + RiscVInstruction::Verbatim { text: START.to_string() }, |
| 19 | + // read syscall |
| 20 | + RiscVInstruction::Addi { dest: RiscVRegister::SP, src: RiscVRegister::SP, imm: -32 }, // sub stack pointer |
| 21 | + RiscVInstruction::Li { dest: RiscVRegister::A7, imm: 63 }, // read syscall # |
| 22 | + RiscVInstruction::Li { dest: RiscVRegister::A2, imm: 32 }, // read 5 bytes |
| 23 | + RiscVInstruction::Mv { dest: RiscVRegister::A1, src: RiscVRegister::SP }, |
| 24 | + RiscVInstruction::Li { dest: RiscVRegister::A0, imm: 0 }, |
| 25 | + RiscVInstruction::ECall, |
| 26 | + // write syscall |
| 27 | + RiscVInstruction::Li { dest: RiscVRegister::A7, imm: 64 }, |
| 28 | + RiscVInstruction::Li { dest: RiscVRegister::A2, imm: 14 }, |
| 29 | + RiscVInstruction::Mv { dest: RiscVRegister::A1, src: RiscVRegister::SP }, |
| 30 | + RiscVInstruction::Li { dest: RiscVRegister::A0, imm: 1 }, |
| 31 | + RiscVInstruction::ECall, |
| 32 | + // exit syscall |
| 33 | + RiscVInstruction::Li { dest: RiscVRegister::A7, imm: 93 }, |
| 34 | + // RiscVInstruction::Li { dest: RiscVRegister::A0, imm: 0 }, |
| 35 | + RiscVInstruction::ECall |
| 36 | + ]; |
| 37 | + |
| 38 | + translate_to_file(riscv_asm, "test_echo.S".to_string()); |
| 39 | + } |
| 40 | +} |
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