translate: map_register_name with semantic meanings

Corrected the translation between registers for our 64 bit architectures.

Author: Samir-Rashid

src/instruction.rs

@@ -248,7 +248,7 @@ pub enum RiscVRegister {
     /// Temporaries
     T2,
     #[strum(serialize = "s0", serialize = "fp")]
-    /// Saved register/frame pointer
+    /// Saved register/frame pointer R29
     S0FP,
     #[strum(serialize = "s1")]
     /// Saved registers
@@ -335,58 +335,60 @@ impl Default for ArmRegister {
 
 /// ARM Registers
 /// https://developer.arm.com/documentation/dui0056/d/using-the-procedure-call-standard/register-roles-and-names/register-names
+/// Image of instructions https://duetorun.com/blog/arm/images/AArch64-registers.png
+///   - https://duetorun.com/blog/20230601/a64-regs/#user_program_registers
 #[derive(Debug, EnumString)]
 pub enum ArmRegisterName {
+    #[strum(serialize = "wzr", serialize = "xzr")]
+    /// Zero register. Hardware special.
+    Zero,
     #[strum(serialize = "pc")]
-    /// Program counter.
+    /// Program counter. Hardware special register.
     Pc,
-    #[strum(serialize = "lr")]
-    /// Link register.
-    Lr,
     #[strum(serialize = "sp")]
-    /// Stack pointer.
+    /// Stack pointer. Hardware special register.
     Sp,
-    #[strum(serialize = "ip")]
-    /// Intra-procedure-call scratch register.
-    Ip,
-    #[strum(serialize = "v8")]
-    /// ARM-state variable register 8.
-    V8,
-    #[strum(serialize = "sl")]
-    /// ARM-state variable register 7. Stack limit pointer in stack-checked variants.
-    Sl,
-    #[strum(serialize = "sb")]
-    /// ARM-state variable register 6. Static base in RWPI variants.
-    Sb,
-    #[strum(serialize = "v5")]
-    /// ARM-state variable register 5.
-    V5,
-    #[strum(serialize = "v4")]
-    /// Variable register 4.
-    V4,
-    #[strum(serialize = "v3")]
-    /// Variable register 3.
-    V3,
-    #[strum(serialize = "v2")]
-    /// Variable register 2.
-    V2,
-    #[strum(serialize = "v1")]
-    /// Variable register 1.
-    V1,
-    #[strum(serialize = "a4")]
-    /// Argument/result/scratch register 4.
-    A4,
-    #[strum(serialize = "a3")]
-    /// Argument/result/scratch register 3.
-    A3,
-    #[strum(serialize = "a2")]
-    /// Argument/result/scratch register 2.
-    A2,
-    #[strum(serialize = "a1")]
-    /// Argument/result/scratch register 1.
-    A1,
-    #[strum(serialize = "wzr", serialize = "xzr")]
-    Zero,
+    #[strum(serialize = "lr")]
+    /// Link register. X30. Hardware special register.
+    Lr,
+    // Parameter passing and/or scratch registers (volatile)
+    X0,
+    X1,
+    X2,
+    X3,
+    X4,
+    X5,
+    X6,
+    X7,
+    // Caller-Saved scratch registers (volatile)
+    /// XR
+    X8,
+    X9,
+    X10,
+    X11,
+    X12,
+    X13,
+    X14,
+    X15,
+    /// IP0
+    X16,
+    /// IP1
+    X17,
+    /// PR
+    X18,
+    // Caller-Saved registers (non-volatile)
+    X19,
+    X20,
+    X21,
+    X22,
+    X23,
+    X24,
+    X25,
+    X26,
+    X27,
+    X28,
+    /// FP
+    X29,
 }
 
 impl Default for ArmRegisterName {

src/translate.rs

@@ -109,10 +109,43 @@ fn map_register(riscv_reg: RiscVRegister, riscv_width: &RiscVWidth) -> ArmRegist
     }
 }
 
+/// Semantic meaning of registers
+/// https://riscv.org/wp-content/uploads/2024/12/riscv-calling.pdf#page=3
 fn map_register_name(riscv_reg: RiscVRegister) -> ArmRegisterName {
-    // todo!()
-        // FIXME: do real implementation
-    ArmRegisterName::A1
+    match riscv_reg {
+        RiscVRegister::X0 => ArmRegisterName::Zero,
+        RiscVRegister::RA => ArmRegisterName::Lr,
+        RiscVRegister::SP => ArmRegisterName::Sp,
+        RiscVRegister::GP => ArmRegisterName::X0,
+        RiscVRegister::TP => ArmRegisterName::X1,
+        RiscVRegister::T0 => ArmRegisterName::X2,
+        RiscVRegister::T1 => ArmRegisterName::X3,
+        RiscVRegister::T2 => ArmRegisterName::X4,
+        RiscVRegister::S0FP => ArmRegisterName::X5,
+        RiscVRegister::S1 => ArmRegisterName::X6,
+        RiscVRegister::A0 => ArmRegisterName::X7,
+        RiscVRegister::A1 => ArmRegisterName::X8,
+        RiscVRegister::A2 => ArmRegisterName::X9,
+        RiscVRegister::A3 => ArmRegisterName::X10,
+        RiscVRegister::A4 => ArmRegisterName::X11,
+        RiscVRegister::A5 => ArmRegisterName::X12,
+        RiscVRegister::A6 => ArmRegisterName::X13,
+        RiscVRegister::A7 => ArmRegisterName::X14,
+        RiscVRegister::S2 => ArmRegisterName::X15,
+        RiscVRegister::S3 => ArmRegisterName::X16,
+        RiscVRegister::S4 => ArmRegisterName::X17,
+        RiscVRegister::S5 => ArmRegisterName::X18,
+        RiscVRegister::S6 => ArmRegisterName::X19,
+        RiscVRegister::S7 => ArmRegisterName::X20,
+        RiscVRegister::S8 => ArmRegisterName::X21,
+        RiscVRegister::S9 => ArmRegisterName::X22,
+        RiscVRegister::S10 => ArmRegisterName::X23,
+        RiscVRegister::S11 => ArmRegisterName::X24,
+        RiscVRegister::T3 => ArmRegisterName::X25,
+        RiscVRegister::T4 => ArmRegisterName::X26,
+        RiscVRegister::T5 => ArmRegisterName::X27,
+        RiscVRegister::T6 => ArmRegisterName::X28,
+    }
 }
 
 fn map_val(riscv_val: RiscVVal, riscv_width: &RiscVWidth) -> ArmVal {