translate: add minimal riscv translation map

Author: Samir-Rashid

src/main.rs

@@ -1,10 +1,11 @@
 use std::fs;
 use std::str::FromStr;
 mod instruction;
-use instruction::Instruction;
+pub mod translate;
+use instruction::RiscVInstruction;
 
 /// Parse a text file into our enum.
-fn parse_asm(asm: &str) -> Vec<Instruction> {
+fn parse_asm(asm: &str) -> Vec<RiscVInstruction> {
     asm.lines()
         .filter_map(|line| {
             // TODO (Samir): Not sure that this will handle assembly labels
@@ -14,7 +15,7 @@ fn parse_asm(asm: &str) -> Vec<Instruction> {
             if parts.is_empty() {
                 None
             } else {
-                Instruction::from_str(parts[0]).ok()
+                RiscVInstruction::from_str(parts[0]).ok()
             }
         })
         .collect()

src/translate.rs

@@ -0,0 +1,19 @@
+use crate::instruction::{ArmInstruction, RiscVInstruction};
+
+/// Run the core logic to match from RISC-V to ARM Instructions.
+
+/// Translate one instruction at a time.
+pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
+    match riscv_instr {
+        RiscVInstruction::Addi => add,
+        RiscVInstruction::Sd => todo!(),
+        RiscVInstruction::Ld => todo!(),
+        RiscVInstruction::Sw => todo!(),
+        RiscVInstruction::Lw => todo!(),
+        RiscVInstruction::Mv => todo!(),
+        RiscVInstruction::Addw => todo!(),
+        RiscVInstruction::SextW => todo!(),
+        RiscVInstruction::Jr => todo!(),
+        RiscVInstruction::Li => todo!(),
+    }
+}