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Samir-RashidSamir-Rashid
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Benchmarking (#6)
1 parent fe3962b commit a2e6ee3

9 files changed

Lines changed: 398 additions & 154 deletions

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‎.gitignore‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,3 +28,4 @@ Cargo.lock
2828
*.bin
2929

3030
.vscode/
31+
test_binary_translate*

‎run.sh‎

Lines changed: 26 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,31 @@
11
#!/usr/bin/env bash
22

33
ASM_FILE=$1
4+
PLATFORM=""
5+
LD_FLAGS=""
6+
BENCHMARKING="false" # "true" to enable
47

8+
if [[ -z "$ASM_FILE" ]]; then
9+
echo "Error: Assembly (.S) file is not passed in."
10+
echo "Usage: ./run.sh test_binary_translate_add.S"
11+
exit 1
12+
fi
513

6-
aarch64-linux-gnu-as $ASM_FILE -o $ASM_FILE.as
7-
aarch64-linux-gnu-ld $ASM_FILE.as -o $ASM_FILE.bin
8-
./$ASM_FILE.bin
9-
echo $?
14+
if [[ "$OSTYPE" == "linux-gnu"* ]]; then
15+
PLATFORM="aarch64-linux-gnu"
16+
fi
17+
18+
if [[ "$OSTYPE" == "darwin"* ]]; then
19+
LD_FLAGS="-lSystem -macosx_version_min 11.3 -L/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/lib"
20+
fi
21+
22+
23+
"$PLATFORM"as "$ASM_FILE" -o "$ASM_FILE".as || { echo "Assembly compilation failed"; exit 1; }
24+
"$PLATFORM"ld "$ASM_FILE".as -o "$ASM_FILE".bin $LD_FLAGS || { echo "Linking failed"; exit 1; }
25+
26+
./"$ASM_FILE".bin
27+
echo "$?"
28+
29+
if [ "$BENCHMARKING" = true ]; then
30+
hyperfine -r 1000 -w 100 -Ni ./"$ASM_FILE".bin
31+
fi

‎src/instruction.rs‎

Lines changed: 95 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ use strum_macros::EnumString;
1515

1616
pub enum RiscVSyscalls {
1717
WRITE,
18-
EXIT
18+
EXIT,
1919
}
2020

2121
impl RiscVSyscalls {
@@ -55,7 +55,7 @@ pub enum RiscVInstruction {
5555
Addl {
5656
dest: RiscVRegister,
5757
src: RiscVRegister,
58-
label: RiscVVal
58+
label: RiscVVal,
5959
},
6060
/// add register
6161
/// either add or addw
@@ -75,12 +75,12 @@ pub enum RiscVInstruction {
7575
Ble {
7676
arg1: RiscVRegister,
7777
arg2: RiscVRegister,
78-
target: RiscVVal
78+
target: RiscVVal,
7979
},
8080
/// call label
8181
#[strum(serialize = "call")]
8282
Call {
83-
label: RiscVVal
83+
label: RiscVVal,
8484
},
8585
/// Store values from register rs2 to memory.
8686
///
@@ -102,15 +102,15 @@ pub enum RiscVInstruction {
102102
},
103103
Directive {
104104
name: String,
105-
operands: String
105+
operands: String,
106106
},
107107
Label {
108-
name: String
108+
name: String,
109109
},
110110
#[strum(serialize = "lui")]
111111
Lui {
112112
dest: RiscVRegister,
113-
src: RiscVVal
113+
src: RiscVVal,
114114
},
115115
// Copy register
116116
// `mv rd, rs1` expands to `addi rd, rs, 0`
@@ -136,7 +136,9 @@ pub enum RiscVInstruction {
136136
},
137137
/// Jump label
138138
#[strum(serialize = "j")]
139-
J { target: RiscVVal },
139+
J {
140+
target: RiscVVal,
141+
},
140142
/// Jump Register
141143
/// Jump to address and place return address in rd.
142144
/// jal rd,offset
@@ -145,7 +147,9 @@ pub enum RiscVInstruction {
145147
/// jr offset => jal x1, offset
146148
///
147149
#[strum(serialize = "jr")]
148-
Jr { target: RiscVRegister },
150+
Jr {
151+
target: RiscVRegister,
152+
},
149153
/// Load Immediate
150154
/// This is a pseudo instruction, so it's not a real instruction
151155
///
@@ -156,12 +160,17 @@ pub enum RiscVInstruction {
156160
/// semantics.
157161
/// https://michaeljclark.github.io/asm.html
158162
#[strum(serialize = "li")]
159-
Li { dest: RiscVRegister, imm: i32 },
163+
Li {
164+
dest: RiscVRegister,
165+
imm: i32,
166+
},
160167
/// System Call
161168
#[strum(serialize = "ecall")]
162169
ECall,
163170
#[strum(serialize = "verbatim")]
164-
Verbatim { text: String },
171+
Verbatim {
172+
text: String,
173+
},
165174
}
166175

167176
impl Default for RiscVInstruction {
@@ -175,7 +184,7 @@ impl Default for RiscVInstruction {
175184

176185
pub enum ArmSyscalls {
177186
WRITE,
178-
EXIT
187+
EXIT,
179188
}
180189

181190
impl ArmSyscalls {
@@ -192,7 +201,7 @@ pub enum ArmVal {
192201
Reg(ArmRegister),
193202
Imm(i32),
194203
RegOffset(ArmRegister, i32),
195-
LabelOffset(String, i32)
204+
LabelOffset(String, i32),
196205
}
197206

198207
impl Default for ArmVal {
@@ -240,26 +249,38 @@ pub enum ArmInstruction {
240249
#[strum(serialize = "adrp")]
241250
Adrp {
242251
dest: ArmRegister,
243-
label: ArmVal
252+
label: ArmVal,
244253
},
245254
/// B Branch R15 := address
246255
#[strum(serialize = "b")]
247-
B { target: ArmVal },
256+
B {
257+
target: ArmVal,
258+
},
248259
/// BLR Xn
249260
#[strum(serialize = "blr")]
250-
Blr { target: ArmRegisterName },
261+
Blr {
262+
target: ArmRegisterName,
263+
},
251264
/// BLE label
252265
#[strum(serialize = "ble")]
253-
Ble { arg1: ArmRegister, arg2: ArmRegister, target: ArmVal },
266+
Ble {
267+
arg1: ArmRegister,
268+
arg2: ArmRegister,
269+
target: ArmVal,
270+
},
254271
/// BL label
255272
#[strum(serialize = "bl")]
256-
Bl {target: ArmVal},
273+
Bl {
274+
target: ArmVal,
275+
},
257276
/// label:
258-
Label { name: String },
277+
Label {
278+
name: String,
279+
},
259280
/// .directive operands
260281
Directive {
261-
name: String,
262-
operands: String
282+
name: String,
283+
operands: String,
263284
},
264285
#[strum(serialize = "ldr")]
265286
Ldr {
@@ -271,7 +292,7 @@ pub enum ArmInstruction {
271292
Mov {
272293
width: ArmWidth,
273294
dest: ArmRegister,
274-
src: ArmVal
295+
src: ArmVal,
275296
},
276297
#[strum(serialize = "ret")]
277298
Ret,
@@ -291,21 +312,37 @@ pub enum ArmInstruction {
291312
},
292313
/// sign extend to word
293314
#[strum(serialize = "sxtw")]
294-
Sxtw { dest: ArmRegister, src: ArmRegister },
295-
/// service call
315+
Sxtw {
316+
dest: ArmRegister,
317+
src: ArmRegister,
318+
},
319+
/// service call
296320
#[strum(serialize = "svc")]
297-
Svc { id: i32 },
321+
Svc {
322+
id: i32,
323+
},
298324
/// compare
299-
Cmp { op1: ArmRegister, op2: ArmVal },
300-
Verbatim { text: String },
325+
Cmp {
326+
op1: ArmRegister,
327+
op2: ArmVal,
328+
},
329+
Verbatim {
330+
text: String,
331+
},
301332
}
302333

303334
impl Default for ArmInstruction {
304335
fn default() -> Self {
305336
ArmInstruction::Mov {
306-
width: ArmWidth::Double,
307-
dest: ArmRegister { width: ArmWidth::Double, name: ArmRegisterName::X0 },
308-
src: ArmVal::Reg(ArmRegister { width: ArmWidth::Double, name: ArmRegisterName::X0 })
337+
width: ArmWidth::Double,
338+
dest: ArmRegister {
339+
width: ArmWidth::Double,
340+
name: ArmRegisterName::X0,
341+
},
342+
src: ArmVal::Reg(ArmRegister {
343+
width: ArmWidth::Double,
344+
name: ArmRegisterName::X0,
345+
}),
309346
}
310347
}
311348
}
@@ -321,8 +358,8 @@ pub enum RiscVVal {
321358
},
322359
LabelOffset {
323360
label: String,
324-
offset: i32
325-
}
361+
offset: i32,
362+
},
326363
}
327364

328365
impl Default for RiscVVal {
@@ -534,65 +571,59 @@ impl Into<String> for ArmInstruction {
534571
ArmInstruction::Adc => todo!(),
535572
ArmInstruction::Add { dest, arg1, arg2 } => {
536573
format!("add {}, {}, {}", dest, arg1, arg2)
537-
},
574+
}
538575
ArmInstruction::And => todo!(),
539576
ArmInstruction::Adrp { dest, label } => {
540577
format!("adrp {}, {}", dest, label)
541578
}
542579
ArmInstruction::B { target } => {
543580
format!("b {}", target)
544-
},
581+
}
545582
ArmInstruction::Ble { arg1, arg2, target } => {
546583
format!("cmp {}, {}\nble {}", arg1, arg2, target)
547-
},
584+
}
548585
ArmInstruction::Blr { target } => {
549586
format!("blr {}", Into::<ArmRegister>::into(target))
550-
},
551-
ArmInstruction::Ldr { width, dest, src } => {
552-
match width {
553-
ArmWidth::Word | ArmWidth::Double => format!("ldr {}, {}", dest, src),
554-
_ => todo!()
555-
}
587+
}
588+
ArmInstruction::Ldr { width, dest, src } => match width {
589+
ArmWidth::Word | ArmWidth::Double => format!("ldr {}, {}", dest, src),
590+
_ => todo!(),
556591
},
557592
ArmInstruction::Mov { width, dest, src } => {
558593
format!("mov {}, {}", dest, src)
559-
},
594+
}
560595
ArmInstruction::Ret => todo!(),
561-
ArmInstruction::Str { width, src, dest } => {
562-
match width {
563-
ArmWidth::Word => format!("str {}, {}", src, dest),
564-
ArmWidth::Double => format!("str {}, {}", src, dest),
565-
_ => todo!("{:?}", width)
566-
}
596+
ArmInstruction::Str { width, src, dest } => match width {
597+
ArmWidth::Word => format!("str {}, {}", src, dest),
598+
ArmWidth::Double => format!("str {}, {}", src, dest),
599+
_ => todo!("{:?}", width),
567600
},
568-
ArmInstruction::Sub { dest, arg1, arg2 } =>
569-
{
601+
ArmInstruction::Sub { dest, arg1, arg2 } => {
570602
format!("sub {}, {}, {}", dest, arg1, arg2)
571-
},
603+
}
572604
ArmInstruction::Sxtw { dest, src } => {
573605
format!("sxtw {}, {}", dest, src)
574-
},
606+
}
575607
ArmInstruction::Bl { target } => {
576608
format!("bl {}", target)
577-
},
609+
}
578610
ArmInstruction::Label { name } => {
579611
format!("{}:", name)
580-
},
612+
}
581613
ArmInstruction::Directive { name, operands } => {
582614
format!(".{} {}", name, operands)
583615
}
584616
ArmInstruction::Svc { id } => {
585617
format!("svc {}", id)
586-
},
618+
}
587619
ArmInstruction::Cmp { op1, op2 } => {
588620
format!("cmp {}, {}", op1, op2)
589621
}
590-
ArmInstruction::Verbatim { text } => text
622+
ArmInstruction::Verbatim { text } => text,
591623
}
592624
}
593625
}
594626

595-
596627
impl Into<String> for ArmRegister {
597628
fn into(self) -> String {
598629
let s: &str = match (self.name, self.width) {
@@ -816,16 +847,16 @@ impl Display for ArmVal {
816847
ArmVal::RegOffset(arm_register, offset) => {
817848
let double_reg = ArmRegister {
818849
name: arm_register.name,
819-
width: ArmWidth::Double
850+
width: ArmWidth::Double,
820851
};
821852
write!(f, "[{}, {}]", double_reg, offset)
822-
},
853+
}
823854
ArmVal::LabelOffset(name, offset) => {
824855
match offset {
825856
0 => write!(f, "{}", name),
826857
9998 => write!(f, "{}", name), // %hi in riscv is adrp with no offset in arm
827858
9999 => write!(f, ":lo12:{}", name), // reserved for 12 low bits of label addr
828-
_ => write!(f, "[{}, {}]", name, offset)
859+
_ => write!(f, "[{}, {}]", name, offset),
829860
}
830861
}
831862
}
@@ -834,6 +865,9 @@ impl Display for ArmVal {
834865

835866
impl Into<ArmRegister> for ArmRegisterName {
836867
fn into(self) -> ArmRegister {
837-
ArmRegister { width: ArmWidth::Double, name: self }
868+
ArmRegister {
869+
width: ArmWidth::Double,
870+
name: self,
871+
}
838872
}
839873
}

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