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Samir-Rashid
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Test loops (#8)
* instruction: split arm, riscv opcodes and add registers * translate: add minimal riscv translation map * meta: rename `test/` -> `tests/` * fibonacci and prime int tests * fix: comment instruction `b`ranch formatting hack, fix riscv asm --------- Co-authored-by: Samir Rashid <Samir-Rashid@godsped.com>
1 parent 9b8c4b6 commit ad53e69

10 files changed

Lines changed: 1247 additions & 2 deletions

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‎src/instruction.rs‎

Lines changed: 99 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,13 +70,50 @@ pub enum RiscVInstruction {
7070
arg1: RiscVRegister,
7171
arg2: RiscVRegister,
7272
},
73+
#[strum(serialize = "subw")]
74+
Sub {
75+
// dest = arg1 - arg2
76+
width: RiscVWidth,
77+
dest: RiscVRegister,
78+
arg1: RiscVRegister,
79+
arg2: RiscVRegister,
80+
},
7381
/// branch if less than or equal
74-
#[strum(serialize = "call")]
82+
#[strum(serialize = "ble")]
7583
Ble {
7684
arg1: RiscVRegister,
7785
arg2: RiscVRegister,
7886
target: RiscVVal,
7987
},
88+
/// branch if greater than or equal
89+
#[strum(serialize = "bge")]
90+
Bge {
91+
arg1: RiscVRegister,
92+
arg2: RiscVRegister,
93+
target: RiscVVal,
94+
},
95+
/// branch if less than
96+
#[strum(serialize = "blt")]
97+
Blt {
98+
arg1: RiscVRegister,
99+
arg2: RiscVRegister,
100+
target: RiscVVal,
101+
},
102+
/// branch if greater than
103+
#[strum(serialize = "bgt")]
104+
Bgt {
105+
arg1: RiscVRegister,
106+
arg2: RiscVRegister,
107+
target: RiscVVal,
108+
},
109+
/// branch if greater than
110+
#[strum(serialize = "bne")]
111+
Bne {
112+
arg1: RiscVRegister,
113+
arg2: RiscVRegister,
114+
target: RiscVVal,
115+
},
116+
/// branch if greater than or equal to
80117
/// call label
81118
#[strum(serialize = "call")]
82119
Call {
@@ -91,6 +128,13 @@ pub enum RiscVInstruction {
91128
src: RiscVRegister,
92129
dest: RiscVVal,
93130
},
131+
/// Rd := Rs << Imm
132+
#[strum(serialize = "Slli")]
133+
Slli {
134+
dest: RiscVRegister,
135+
src: RiscVRegister,
136+
imm: i32
137+
},
94138
/// Loads a value from memory into register rd for RV64I.
95139
///
96140
/// `x[rd] = M[x[rs1] + sext(offset)]`
@@ -268,6 +312,34 @@ pub enum ArmInstruction {
268312
arg2: ArmRegister,
269313
target: ArmVal,
270314
},
315+
/// BGE label
316+
#[strum(serialize = "bge")]
317+
Bge {
318+
arg1: ArmRegister,
319+
arg2: ArmRegister,
320+
target: ArmVal,
321+
},
322+
/// BLT label
323+
#[strum(serialize = "blt")]
324+
Blt {
325+
arg1: ArmRegister,
326+
arg2: ArmRegister,
327+
target: ArmVal,
328+
},
329+
/// BGT label
330+
#[strum(serialize = "bgt")]
331+
Bgt {
332+
arg1: ArmRegister,
333+
arg2: ArmRegister,
334+
target: ArmVal,
335+
},
336+
/// BNE label
337+
#[strum(serialize = "bne")]
338+
Bne {
339+
arg1: ArmRegister,
340+
arg2: ArmRegister,
341+
target: ArmVal,
342+
},
271343
/// BL label
272344
#[strum(serialize = "bl")]
273345
Bl {
@@ -296,6 +368,13 @@ pub enum ArmInstruction {
296368
},
297369
#[strum(serialize = "ret")]
298370
Ret,
371+
/// Rd := Rs << Imm
372+
#[strum(serialize = "Lsl")]
373+
Lsl {
374+
dest: ArmRegister,
375+
src: ArmRegister,
376+
imm: i32
377+
},
299378
/// Str [r2 + offset] = r1
300379
#[strum(serialize = "str")]
301380
Str {
@@ -579,9 +658,25 @@ impl Into<String> for ArmInstruction {
579658
ArmInstruction::B { target } => {
580659
format!("b {}", target)
581660
}
661+
// TODO: Fix these branching instructions need to map to
662+
// multiple instructions. Would be better separation of concerns
663+
// if this was produced by the translation function instead of a
664+
// hack in the string formatting.
582665
ArmInstruction::Ble { arg1, arg2, target } => {
583666
format!("cmp {}, {}\nble {}", arg1, arg2, target)
584667
}
668+
ArmInstruction::Bge { arg1, arg2, target } => {
669+
format!("cmp {}, {}\nbge {}", arg1, arg2, target)
670+
}
671+
ArmInstruction::Blt { arg1, arg2, target } => {
672+
format!("cmp {}, {}\nblt {}", arg1, arg2, target)
673+
}
674+
ArmInstruction::Bgt { arg1, arg2, target } => {
675+
format!("cmp {}, {}\nbgt {}", arg1, arg2, target)
676+
}
677+
ArmInstruction::Bne { arg1, arg2, target } => {
678+
format!("cmp {}, {}\nbne {}", arg1, arg2, target)
679+
}
585680
ArmInstruction::Blr { target } => {
586681
format!("blr {}", Into::<ArmRegister>::into(target))
587682
}
@@ -598,6 +693,9 @@ impl Into<String> for ArmInstruction {
598693
ArmWidth::Double => format!("str {}, {}", src, dest),
599694
_ => todo!("{:?}", width),
600695
},
696+
ArmInstruction::Lsl { dest, src, imm } => {
697+
format!("lsl {}, {}, {}", dest, src, imm)
698+
}
601699
ArmInstruction::Sub { dest, arg1, arg2 } => {
602700
format!("sub {}, {}, {}", dest, arg1, arg2)
603701
}

‎src/translate.rs‎

Lines changed: 89 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,38 @@ pub fn translate(riscv_instr: RiscVInstruction) -> Vec<ArmInstruction> {
4444
target: map_val(target, &width),
4545
}
4646
}],
47+
RiscVInstruction::Bge { arg1, arg2, target } => vec![{
48+
let width = RiscVWidth::Double;
49+
ArmInstruction::Bge {
50+
arg1: map_register(arg1, &width),
51+
arg2: map_register(arg2, &width),
52+
target: map_val(target, &width),
53+
}
54+
}],
55+
RiscVInstruction::Blt { arg1, arg2, target } => vec![{
56+
let width = RiscVWidth::Double;
57+
ArmInstruction::Blt {
58+
arg1: map_register(arg1, &width),
59+
arg2: map_register(arg2, &width),
60+
target: map_val(target, &width),
61+
}
62+
}],
63+
RiscVInstruction::Bgt { arg1, arg2, target } => vec![{
64+
let width = RiscVWidth::Double;
65+
ArmInstruction::Bgt {
66+
arg1: map_register(arg1, &width),
67+
arg2: map_register(arg2, &width),
68+
target: map_val(target, &width),
69+
}
70+
}],
71+
RiscVInstruction::Bne { arg1, arg2, target } => vec![{
72+
let width = RiscVWidth::Double;
73+
ArmInstruction::Bne {
74+
arg1: map_register(arg1, &width),
75+
arg2: map_register(arg2, &width),
76+
target: map_val(target, &width),
77+
}
78+
}],
4779
RiscVInstruction::J { target } => vec![ArmInstruction::B {
4880
target: map_val(target, &RiscVWidth::Double),
4981
}],
@@ -52,6 +84,14 @@ pub fn translate(riscv_instr: RiscVInstruction) -> Vec<ArmInstruction> {
5284
src: map_register(src, &width),
5385
dest: map_val(dest, &width),
5486
}],
87+
RiscVInstruction::Slli { dest, src, imm } => {
88+
let width = RiscVWidth::Double;
89+
vec![ArmInstruction::Lsl {
90+
dest: map_register(dest, &width),
91+
src: map_register(src, &width),
92+
imm: imm
93+
}]
94+
},
5595
RiscVInstruction::L { width, dest, src } => vec![ArmInstruction::Ldr {
5696
width: map_width(&width),
5797
dest: map_register(dest, &width),
@@ -101,7 +141,55 @@ pub fn translate(riscv_instr: RiscVInstruction) -> Vec<ArmInstruction> {
101141
name: map_register_name(arg2),
102142
}),
103143
}],
104-
RiscVWidth::Double => sorry!(),
144+
RiscVWidth::Double => vec![ArmInstruction::Add {
145+
dest: ArmRegister {
146+
width: ArmWidth::Double,
147+
name: map_register_name(dest),
148+
},
149+
arg1: ArmRegister {
150+
width: ArmWidth::Double,
151+
name: map_register_name(arg1),
152+
},
153+
arg2: ArmVal::Reg(ArmRegister {
154+
width: ArmWidth::Double,
155+
name: map_register_name(arg2),
156+
}),
157+
}],
158+
},
159+
RiscVInstruction::Sub {
160+
width,
161+
dest,
162+
arg1,
163+
arg2,
164+
} => match width {
165+
RiscVWidth::Word => vec![ArmInstruction::Sub {
166+
dest: ArmRegister {
167+
width: ArmWidth::Word,
168+
name: map_register_name(dest),
169+
},
170+
arg1: ArmRegister {
171+
width: ArmWidth::Word,
172+
name: map_register_name(arg1),
173+
},
174+
arg2: ArmVal::Reg(ArmRegister {
175+
width: ArmWidth::Word,
176+
name: map_register_name(arg2),
177+
}),
178+
}],
179+
RiscVWidth::Double => vec![ArmInstruction::Sub {
180+
dest: ArmRegister {
181+
width: ArmWidth::Double,
182+
name: map_register_name(dest),
183+
},
184+
arg1: ArmRegister {
185+
width: ArmWidth::Double,
186+
name: map_register_name(arg1),
187+
},
188+
arg2: ArmVal::Reg(ArmRegister {
189+
width: ArmWidth::Double,
190+
name: map_register_name(arg2),
191+
}),
192+
}],
105193
},
106194
RiscVInstruction::SextW { dest, src } => vec![ArmInstruction::Sxtw {
107195
dest: ArmRegister {

‎src/utils.rs‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,27 @@ _main:
1919
main:
2020
"#;
2121

22+
pub const START_NO_MAIN: &str = r#"
23+
.text
24+
25+
.global _start
26+
.global _main
27+
28+
.balign 4
29+
_start:
30+
bl main
31+
mov x8, #93
32+
svc #0
33+
"#;
34+
35+
/// Assembler directives for main only, used when another
36+
/// function defined before main
37+
pub const START_MAIN: &str = r#"
38+
.balign 4
39+
_main:
40+
main:
41+
"#;
42+
2243
pub fn translate_to_file(instrs: Vec<RiscVInstruction>, path: String) {
2344
let arm_instrs = translate_instrs(instrs);
2445
let mut contents = String::new();

‎tests/fib/fib.arm.s‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
2+
.text
3+
4+
.global _start
5+
.global _main
6+
7+
.balign 4
8+
_start:
9+
bl main
10+
mov x8, #93
11+
svc #0
12+
13+
.balign 4
14+
_main:
15+
main:
16+
17+
sub sp, sp, 64
18+
str x29, [sp, 56]
19+
add x29, sp, 64
20+
str xzr, [x29, -64]
21+
str xzr, [x29, -56]
22+
str xzr, [x29, -48]
23+
str xzr, [x29, -40]
24+
str xzr, [x29, -32]
25+
mov x5, 1
26+
str w5, [x29, -60]
27+
mov x5, 2
28+
str w5, [x29, -20]
29+
b .L2
30+
.L3:
31+
ldr w5, [x29, -20]
32+
sub x5, x5, 1
33+
sxtw x5, w5
34+
lsl x5, x5, 2
35+
sub x5, x5, 16
36+
add x5, x5, x29
37+
ldr x4, [x5, -48]
38+
ldr x5, [x29, -20]
39+
sub x5, x5, 2
40+
sxtw x5, w5
41+
lsl x5, x5, 2
42+
sub x5, x5, 16
43+
add x5, x5, x29
44+
ldr x5, [x5, -48]
45+
add x5, x4, x5
46+
sxtw x4, w5
47+
ldr x5, [x29, -20]
48+
lsl x5, x5, 2
49+
sub x5, x5, 16
50+
add x5, x5, x29
51+
str x4, [x5, -48]
52+
ldr x5, [x29, -20]
53+
add x5, x5, 1
54+
str w5, [x29, -20]
55+
.L2:
56+
ldr x5, [x29, -20]
57+
sxtw x4, w5
58+
mov x5, 9
59+
cmp x4, x5
60+
ble .L3
61+
ldr w5, [x29, -28]
62+
add x0, x5, 0
63+
ldr x29, [sp, 56]
64+
add sp, sp, 64
65+
blr lr

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