basic control flow

Author: trdavidt

src/instruction.rs

@@ -56,6 +56,13 @@ pub enum RiscVInstruction {
         arg1: RiscVRegister,
         arg2: RiscVRegister,
     },
+    /// branch if less than or equal
+    #[strum(serialize = "call")]
+    Ble {
+        arg1: RiscVRegister,
+        arg2: RiscVRegister,
+        target: RiscVVal
+    },
     /// call label
     #[strum(serialize = "call")]
     Call {
@@ -113,6 +120,9 @@ pub enum RiscVInstruction {
         dest: RiscVRegister,
         src: RiscVRegister,
     },
+    /// Jump label
+    #[strum(serialize = "j")]
+    J { target: RiscVVal },
     /// Jump Register
     /// Jump to address and place return address in rd.
     /// jal rd,offset
@@ -201,10 +211,13 @@ pub enum ArmInstruction {
     },
     /// B Branch R15 := address
     #[strum(serialize = "b")]
-    B,
+    B { target: ArmVal },
     /// BLR Xn
     #[strum(serialize = "blr")]
     Blr { target: ArmRegisterName },
+    /// BLE label
+    #[strum(serialize = "ble")]
+    Ble { arg1: ArmRegister, arg2: ArmRegister, target: ArmVal },
     /// BL label
     #[strum(serialize = "bl")]
     Bl {target: ArmVal},
@@ -250,7 +263,11 @@ pub enum ArmInstruction {
 
 impl Default for ArmInstruction {
     fn default() -> Self {
-        ArmInstruction::B
+        ArmInstruction::Mov {
+            width: ArmWidth::Double, 
+            dest: ArmRegister { width: ArmWidth::Double, name: ArmRegisterName::X0 },
+            src: ArmVal::Reg(ArmRegister { width: ArmWidth::Double, name: ArmRegisterName::X0 })
+        }
     }
 }
 
@@ -483,7 +500,12 @@ impl Into<String> for ArmInstruction {
             ArmInstruction::Adrp { dest, label } => {
                 format!("adrp {}, {}", dest, label)
             }
-            ArmInstruction::B => todo!(),
+            ArmInstruction::B { target } => {
+                format!("b {}", target)
+            },
+            ArmInstruction::Ble { arg1, arg2, target } => {
+                format!("cmp {}, {}\n blt {}", arg1, arg2, target)
+            },
             ArmInstruction::Blr { target } => {
                 format!("blr {}", Into::<ArmRegister>::into(target))
             },

src/translate.rs

@@ -35,7 +35,18 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
                     arg2: ArmVal::Imm(imm.abs()),
                 }
             }
-        }
+        },
+        RiscVInstruction::Ble { arg1, arg2, target } => {
+            let width = RiscVWidth::Double;
+            ArmInstruction::Ble {
+                arg1: map_register(arg1, &width),
+                arg2: map_register(arg2, &width),
+                target: map_val(target, &width)
+            }
+        },
+        RiscVInstruction::J { target } => ArmInstruction::B {
+            target: map_val(target, &RiscVWidth::Double)
+        },
         RiscVInstruction::S { width, src, dest } => ArmInstruction::Str {
             width: map_width(&width),
             src: map_register(src, &width),

tests/test_translation.rs

@@ -229,4 +229,33 @@ mod tests {
 
         translate_to_file(riscv_asm, "test_binary_translate_write.S".to_string());
     }
+
+    #[test]
+    fn test_loop() {
+        let riscv_asm: Vec<RiscVInstruction> = vec![
+            RiscVInstruction::Addi { dest: RiscVRegister::SP, src: RiscVRegister::SP, imm: -32 },
+            RiscVInstruction::S { width: RiscVWidth::Double, src: RiscVRegister::S0FP, dest: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: 24 } },
+            RiscVInstruction::Addi { dest: RiscVRegister::SP, src: RiscVRegister::SP, imm: 32 },
+            RiscVInstruction::S { width: RiscVWidth::Word, src: RiscVRegister::X0, dest: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: -20 } },
+            RiscVInstruction::J { target: RiscVVal::LabelOffset { label: ".L2".to_string(), offset: 0 }},
+            RiscVInstruction::Label { name: ".L3".to_string() },
+            RiscVInstruction::L { width: RiscVWidth::Word, dest: RiscVRegister::A5, src: RiscVVal::Offset { register:RiscVRegister::S0FP, offset: -24 } },
+            RiscVInstruction::Addi { dest: RiscVRegister::A5, src: RiscVRegister::A5, imm: 1 },
+            RiscVInstruction::S { width: RiscVWidth::Word, src: RiscVRegister::A5, dest: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: -24 } },
+            RiscVInstruction::L { width: RiscVWidth::Word, dest: RiscVRegister::A5, src: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: -20 } },
+            RiscVInstruction::Addi { dest: RiscVRegister::A5, src: RiscVRegister::A5, imm: 1 },
+            RiscVInstruction::S { width: RiscVWidth::Word, src: RiscVRegister::A5, dest: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: -20 } },
+            RiscVInstruction::Label { name: ".L2".to_string() },
+            RiscVInstruction::L { width: RiscVWidth::Word, dest: RiscVRegister::A5, src: RiscVVal::Offset { register:RiscVRegister::S0FP, offset: -20 } },
+            RiscVInstruction::SextW { dest: RiscVRegister::A4, src: RiscVRegister::A5 },
+            RiscVInstruction::Li { dest:RiscVRegister::A5, imm: 4 },
+            RiscVInstruction::Ble { arg1: RiscVRegister::A4, arg2: RiscVRegister::A5, target: RiscVVal::LabelOffset { label: ".L3".to_string(), offset: 0 } },
+            RiscVInstruction::L { width: RiscVWidth::Word, dest: RiscVRegister::A5, src: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: -24 } },
+            RiscVInstruction::Mv { dest: RiscVRegister::A0, src: RiscVRegister::A5 },
+            RiscVInstruction::L { width: RiscVWidth::Double, dest: RiscVRegister::S0FP, src: RiscVVal::Offset { register: RiscVRegister::S0FP, offset: 24 } },
+            RiscVInstruction::Addi { dest: RiscVRegister::SP, src: RiscVRegister::SP, imm: 32 },
+            RiscVInstruction::Jr { target: RiscVRegister::RA },
+        ];
+        translate_to_file(riscv_asm, "test_binary_translate_loop.S".to_string());
+    }
 }