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Merge branch 'main' of github.com:Samir-Rashid/binary-room
2 parents 1f770cc + 9b8c4b6 commit e157c93

9 files changed

Lines changed: 194 additions & 3 deletions

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‎src/utils.rs‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,5 +27,6 @@ pub fn translate_to_file(instrs: Vec<RiscVInstruction>, path: String) {
2727
contents.push_str(&x);
2828
contents.push_str("\n");
2929
}
30-
fs::write(path, contents).expect("Unable to write file");
30+
fs::write(&path, contents).expect("Unable to write file");
31+
println!("Saved ARM assembly to {}", path);
3132
}

test_binary_translate_add.S renamed to tests/add/add.arm.s

File renamed without changes.

tests/binaries/add.riscv.s renamed to tests/add/add.riscv.s

File renamed without changes.

‎tests/add/test_add.rs‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
#[cfg(test)]
2+
mod tests {
3+
use binary_room::instruction::*;
4+
use binary_room::translate::*;
5+
use binary_room::utils;
6+
use binary_room::utils::translate_to_file;
7+
use binary_room::utils::START;
8+
9+
#[test]
10+
fn test_binary_translate() {
11+
let riscv_asm: Vec<RiscVInstruction> = vec![
12+
RiscVInstruction::Verbatim { text: START.to_string() },
13+
RiscVInstruction::Addi {
14+
dest: RiscVRegister::SP,
15+
src: RiscVRegister::SP,
16+
imm: -32,
17+
},
18+
RiscVInstruction::S {
19+
width: RiscVWidth::Double,
20+
src: RiscVRegister::RA,
21+
dest: RiscVVal::Offset {
22+
register: RiscVRegister::SP,
23+
offset: 24,
24+
},
25+
},
26+
RiscVInstruction::S {
27+
width: RiscVWidth::Double,
28+
src: RiscVRegister::S0FP,
29+
dest: RiscVVal::Offset {
30+
register: RiscVRegister::SP,
31+
offset: 16,
32+
},
33+
},
34+
RiscVInstruction::Addi {
35+
dest: RiscVRegister::S0FP,
36+
src: RiscVRegister::SP,
37+
imm: 32,
38+
},
39+
RiscVInstruction::Li {
40+
dest: RiscVRegister::A5,
41+
imm: 3,
42+
},
43+
RiscVInstruction::S {
44+
width: RiscVWidth::Word,
45+
src: RiscVRegister::A5,
46+
dest: RiscVVal::Offset {
47+
register: RiscVRegister::S0FP,
48+
offset: -20,
49+
},
50+
},
51+
RiscVInstruction::Li {
52+
dest: RiscVRegister::A5,
53+
imm: 4,
54+
},
55+
RiscVInstruction::S {
56+
width: RiscVWidth::Word,
57+
src: RiscVRegister::A5,
58+
dest: RiscVVal::Offset {
59+
register: RiscVRegister::S0FP,
60+
offset: -24,
61+
},
62+
},
63+
RiscVInstruction::L {
64+
width: RiscVWidth::Word,
65+
dest: RiscVRegister::A5,
66+
src: RiscVVal::Offset {
67+
register: RiscVRegister::S0FP,
68+
offset: -20,
69+
},
70+
},
71+
RiscVInstruction::Mv {
72+
dest: RiscVRegister::A4,
73+
src: RiscVRegister::A5,
74+
},
75+
RiscVInstruction::L {
76+
width: RiscVWidth::Word,
77+
dest: RiscVRegister::A5,
78+
src: RiscVVal::Offset {
79+
register: RiscVRegister::S0FP,
80+
offset: -24,
81+
},
82+
},
83+
RiscVInstruction::Add {
84+
width: RiscVWidth::Word,
85+
dest: RiscVRegister::A5,
86+
arg1: RiscVRegister::A4,
87+
arg2: RiscVRegister::A5,
88+
},
89+
RiscVInstruction::SextW {
90+
dest: RiscVRegister::A5,
91+
src: RiscVRegister::A5,
92+
},
93+
RiscVInstruction::Mv {
94+
dest: RiscVRegister::A0,
95+
src: RiscVRegister::A5,
96+
},
97+
RiscVInstruction::L {
98+
width: RiscVWidth::Double,
99+
dest: RiscVRegister::RA,
100+
src: RiscVVal::Offset {
101+
register: RiscVRegister::SP,
102+
offset: 24,
103+
},
104+
},
105+
RiscVInstruction::L {
106+
width: RiscVWidth::Double,
107+
dest: RiscVRegister::S0FP,
108+
src: RiscVVal::Offset {
109+
register: RiscVRegister::SP,
110+
offset: 16,
111+
},
112+
},
113+
RiscVInstruction::Addi {
114+
dest: RiscVRegister::SP,
115+
src: RiscVRegister::SP,
116+
imm: 32,
117+
},
118+
RiscVInstruction::Jr {
119+
target: RiscVRegister::RA,
120+
},
121+
];
122+
123+
translate_to_file(riscv_asm, "./tests/add/add.arm.s".to_string());
124+
}
125+
}

‎tests/echo/echo.arm.s‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
2+
.text
3+
4+
.global _start
5+
.global _main
6+
7+
.balign 4
8+
_start:
9+
bl main
10+
mov x8, #93
11+
svc #0
12+
13+
.balign 4
14+
_main:
15+
main:
16+
17+
sub sp, sp, 32
18+
mov x8, 63
19+
mov x2, 32
20+
add x1, sp, 0
21+
mov x0, 0
22+
svc 0
23+
mov x8, 64
24+
mov x2, 14
25+
add x1, sp, 0
26+
mov x0, 1
27+
svc 0
28+
mov x8, 93
29+
svc 0

tests/test_echo.rs renamed to tests/echo/test_echo.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,6 @@ mod tests {
6868
RiscVInstruction::ECall,
6969
];
7070

71-
translate_to_file(riscv_asm, "test_binary_translate_echo.S".to_string());
71+
translate_to_file(riscv_asm, "./tests/echo/echo.arm.s".to_string());
7272
}
7373
}

‎tests/print/print.arm.s‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
2+
.buf:
3+
.string "hello world\n"
4+
5+
6+
.text
7+
8+
.global _start
9+
.global _main
10+
11+
.balign 4
12+
_start:
13+
bl main
14+
mov x8, #93
15+
svc #0
16+
17+
.balign 4
18+
_main:
19+
main:
20+
21+
mov x8, 64
22+
mov x2, 14
23+
adrp x0, .buf
24+
add x1, x0, :lo12:.buf
25+
mov x0, 1
26+
svc 0
27+
mov x8, 93
28+
svc 0

tests/test_print.rs renamed to tests/print/test_print.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,6 @@ mod tests {
5858
RiscVInstruction::ECall,
5959
];
6060

61-
translate_to_file(riscv_asm, "test_binary_translate_print.S".to_string());
61+
translate_to_file(riscv_asm, "./tests/print/print.arm.s".to_string());
6262
}
6363
}

‎tests/tests.rs‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
#[path = "add/test_add.rs"]
2+
mod add;
3+
4+
#[path = "echo/test_echo.rs"]
5+
mod echo;
6+
7+
#[path = "print/test_print.rs"]
8+
mod print;

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