organize add test

Author: atar13

src/utils.rs

@@ -27,5 +27,6 @@ pub fn translate_to_file(instrs: Vec<RiscVInstruction>, path: String) {
         contents.push_str(&x);
         contents.push_str("\n");
     }
-    fs::write(path, contents).expect("Unable to write file");
+    fs::write(&path, contents).expect("Unable to write file");
+    println!("Saved ARM assembly to {}", path);
 }

test_binary_translate_add.S tests/add/add.arm.stest_binary_translate_add.S renamed to tests/add/add.arm.s

@@ -2,16 +2,12 @@
 .text
 
 .global _start
-.global _main
 
-.balign 4
 _start:
 bl main
 mov x8, #93
 svc #0
 
-.balign 4
-_main:
 main:
 
 sub sp, sp, 32

tests/binaries/add.riscv.s tests/add/add.riscv.stests/binaries/add.riscv.s renamed to tests/add/add.riscv.s

@@ -0,0 +1,125 @@
+#[cfg(test)]
+mod tests {
+    use binary_room::instruction::*;
+    use binary_room::translate::*;
+    use binary_room::utils;
+    use binary_room::utils::translate_to_file;
+    use binary_room::utils::START;
+
+    #[test]
+    fn test_binary_translate() {
+        let riscv_asm: Vec<RiscVInstruction> = vec![
+            RiscVInstruction::Verbatim { text: START.to_string() },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::SP,
+                src: RiscVRegister::SP,
+                imm: -32,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Double,
+                src: RiscVRegister::RA,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 24,
+                },
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Double,
+                src: RiscVRegister::S0FP,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 16,
+                },
+            },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::S0FP,
+                src: RiscVRegister::SP,
+                imm: 32,
+            },
+            RiscVInstruction::Li {
+                dest: RiscVRegister::A5,
+                imm: 3,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Word,
+                src: RiscVRegister::A5,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -20,
+                },
+            },
+            RiscVInstruction::Li {
+                dest: RiscVRegister::A5,
+                imm: 4,
+            },
+            RiscVInstruction::S {
+                width: RiscVWidth::Word,
+                src: RiscVRegister::A5,
+                dest: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -24,
+                },
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -20,
+                },
+            },
+            RiscVInstruction::Mv {
+                dest: RiscVRegister::A4,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::S0FP,
+                    offset: -24,
+                },
+            },
+            RiscVInstruction::Add {
+                width: RiscVWidth::Word,
+                dest: RiscVRegister::A5,
+                arg1: RiscVRegister::A4,
+                arg2: RiscVRegister::A5,
+            },
+            RiscVInstruction::SextW {
+                dest: RiscVRegister::A5,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::Mv {
+                dest: RiscVRegister::A0,
+                src: RiscVRegister::A5,
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Double,
+                dest: RiscVRegister::RA,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 24,
+                },
+            },
+            RiscVInstruction::L {
+                width: RiscVWidth::Double,
+                dest: RiscVRegister::S0FP,
+                src: RiscVVal::Offset {
+                    register: RiscVRegister::SP,
+                    offset: 16,
+                },
+            },
+            RiscVInstruction::Addi {
+                dest: RiscVRegister::SP,
+                src: RiscVRegister::SP,
+                imm: 32,
+            },
+            RiscVInstruction::Jr {
+                target: RiscVRegister::RA,
+            },
+        ];
+
+        translate_to_file(riscv_asm, "./tests/add/add.arm.s".to_string());
+    }
+}

tests/add/test_add.rs

@@ -0,0 +1,3 @@
+
+#[path = "add/test_add.rs"]
+mod add;