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Samir-RashidSamir-Rashid
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test: run add and print thousands of times
To support better benchmarking, loop the `main` function thousands of times.
1 parent 56d1f6b commit ee0e785

9 files changed

Lines changed: 155 additions & 18 deletions

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‎src/utils.rs‎

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,68 @@ use std::fs;
22

33
use crate::{instruction::RiscVInstruction, translate::translate_instrs};
44

5-
pub const START: &str = r#"
5+
/// Loop main() 10,000 times. Uses a3.
6+
pub const RISCV_LOOP_START: &str = r#"
7+
.text
8+
9+
.global _start
10+
.global _main
11+
12+
.balign 4 # not sure if these are needed for RISC-V
13+
_start:
14+
# while i < 10,000
15+
li a3, 10000
16+
.loop:
17+
addi a3, a3, -1
18+
ble a3, x0, .end
19+
20+
# main()
21+
jal ra, main
22+
23+
# while loop
24+
j .loop
25+
.end:
26+
# exit(0)
27+
li a7,93
28+
ecall
29+
30+
.balign 4
31+
_main:
32+
main:
33+
"#;
34+
35+
/// Loop main() 10,000 times. Uses x3
36+
pub const ARM_LOOP_START: &str = r#"
37+
.text
38+
39+
.global _start
40+
.global _main
41+
42+
.balign 4
43+
_start:
44+
# i = 10,000
45+
mov x3, #10000
46+
# while i > 0
47+
.loop:
48+
sub x3, x3, 1
49+
50+
cmp x3, xzr
51+
ble .end
52+
53+
# main()
54+
bl main
55+
56+
b .loop
57+
.end:
58+
mov x8, #93
59+
svc #0
60+
61+
.balign 4
62+
_main:
63+
main:
64+
"#;
65+
66+
pub const ARM_START: &str = r#"
667
.text
768
869
.global _start

‎tests/add/add.arm.s‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,20 @@
66

77
.balign 4
88
_start:
9+
# i = 10,000
10+
mov x3, #10000
11+
# while i > 0
12+
.loop:
13+
sub x3, x3, 1
14+
15+
cmp x3, xzr
16+
ble .end
17+
18+
# main()
919
bl main
20+
21+
b .loop
22+
.end:
1023
mov x8, #93
1124
svc #0
1225

‎tests/add/add.riscv.s‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,25 @@
1+
.text
2+
3+
.global _start
4+
.global _main
5+
6+
.balign 4 # not sure if these are needed for RISC-V
7+
_start:
8+
# while i < 10,000
9+
li a3, 10000
10+
.loop:
11+
addi a3, a3, -1
12+
ble a3, x0, .end
13+
14+
# main()
15+
jal ra, main
16+
17+
# while loop
18+
j .loop
19+
.end:
20+
# exit(0)
21+
li a7,93
22+
ecall
123
main:
224
addi sp,sp,-32
325
sd ra,24(sp)

‎tests/add/test_add.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,13 @@ mod tests {
44
use binary_room::translate::*;
55
use binary_room::utils;
66
use binary_room::utils::translate_to_file;
7-
use binary_room::utils::START;
7+
use binary_room::utils::ARM_LOOP_START;
88

99
#[test]
1010
fn test_binary_translate() {
1111
let riscv_asm: Vec<RiscVInstruction> = vec![
1212
RiscVInstruction::Verbatim {
13-
text: START.to_string(),
13+
text: ARM_LOOP_START.to_string(),
1414
},
1515
RiscVInstruction::Addi {
1616
dest: RiscVRegister::SP,

‎tests/echo/test_echo.rs‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ mod tests {
44
use binary_room::translate::*;
55
use binary_room::utils;
66
use binary_room::utils::translate_to_file;
7-
use binary_room::utils::START;
7+
use binary_room::utils::ARM_START;
88

99
const buf: &str = r#"
1010
.buf:
@@ -16,7 +16,7 @@ mod tests {
1616
let riscv_asm: Vec<RiscVInstruction> = vec![
1717
// RiscVInstruction::Verbatim { text: buf.to_string() },
1818
RiscVInstruction::Verbatim {
19-
text: START.to_string(),
19+
text: ARM_START.to_string(),
2020
},
2121
// read syscall
2222
RiscVInstruction::Addi {

‎tests/print/print.arm.s‎

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11

2-
.buf:
2+
buf:
33
.string "hello world\n"
44

55

@@ -18,11 +18,19 @@ svc #0
1818
_main:
1919
main:
2020

21+
mov x3, 1000
22+
.loop:
23+
sub x3, x3, 1
24+
cmp x3, xzr
25+
ble .end
2126
mov x8, 64
2227
mov x2, 14
23-
adrp x0, .buf
24-
add x1, x0, :lo12:.buf
28+
adrp x0, buf
29+
add x1, x0, :lo12:buf
2530
mov x0, 1
2631
svc 0
32+
b .loop
33+
.end:
2734
mov x8, 93
35+
mov x0, 0
2836
svc 0

‎tests/print/print.riscv.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
buf:
2-
.string "Hello world!"
2+
.string "Hello world!\n"
33

44
.section .text
55
.globl _start

‎tests/print/test_print.rs‎

Lines changed: 39 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@ mod tests {
44
use binary_room::translate::*;
55
use binary_room::utils;
66
use binary_room::utils::translate_to_file;
7-
use binary_room::utils::START;
7+
use binary_room::utils::ARM_START;
88

99
const buf: &str = r#"
10-
.buf:
10+
buf:
1111
.string "hello world\n"
1212
"#;
1313

@@ -18,7 +18,28 @@ mod tests {
1818
text: buf.to_string(),
1919
},
2020
RiscVInstruction::Verbatim {
21-
text: START.to_string(),
21+
text: ARM_START.to_string(),
22+
},
23+
// While i < 1000
24+
RiscVInstruction::Li {
25+
dest: RiscVRegister::A3,
26+
imm: 1000,
27+
},
28+
RiscVInstruction::Label {
29+
name: ".loop".to_string(),
30+
},
31+
RiscVInstruction::Addi {
32+
dest: RiscVRegister::A3,
33+
src: RiscVRegister::A3,
34+
imm: -1,
35+
},
36+
RiscVInstruction::Ble {
37+
arg1: RiscVRegister::A3,
38+
arg2: RiscVRegister::X0,
39+
target: RiscVVal::LabelOffset {
40+
label: ".end".to_string(),
41+
offset: 0,
42+
},
2243
},
2344
// write syscall
2445
RiscVInstruction::Li {
@@ -32,15 +53,15 @@ mod tests {
3253
RiscVInstruction::Lui {
3354
dest: RiscVRegister::A0,
3455
src: RiscVVal::LabelOffset {
35-
label: ".buf".to_string(),
56+
label: "buf".to_string(),
3657
offset: 9998,
3758
},
3859
},
3960
RiscVInstruction::Addl {
4061
dest: RiscVRegister::A1,
4162
src: RiscVRegister::A0,
4263
label: RiscVVal::LabelOffset {
43-
label: ".buf".to_string(),
64+
label: "buf".to_string(),
4465
offset: 9999,
4566
},
4667
},
@@ -49,12 +70,24 @@ mod tests {
4970
imm: 1,
5071
},
5172
RiscVInstruction::ECall,
73+
RiscVInstruction::J {
74+
target: RiscVVal::LabelOffset {
75+
label: ".loop".to_string(),
76+
offset: 0,
77+
},
78+
},
79+
RiscVInstruction::Label {
80+
name: ".end".to_string(),
81+
},
5282
// exit syscall
5383
RiscVInstruction::Li {
5484
dest: RiscVRegister::A7,
5585
imm: 93,
5686
},
57-
// RiscVInstruction::Li { dest: RiscVRegister::A0, imm: 0 },
87+
RiscVInstruction::Li {
88+
dest: RiscVRegister::A0,
89+
imm: 0,
90+
},
5891
RiscVInstruction::ECall,
5992
];
6093

‎tests/test_translation.rs‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,13 +4,13 @@ mod tests {
44
use binary_room::translate::*;
55
use binary_room::utils;
66
use binary_room::utils::translate_to_file;
7-
use binary_room::utils::START;
7+
use binary_room::utils::ARM_START;
88

99
#[test]
1010
fn test_binary_translate() {
1111
let riscv_asm: Vec<RiscVInstruction> = vec![
1212
RiscVInstruction::Verbatim {
13-
text: START.to_string(),
13+
text: ARM_START.to_string(),
1414
},
1515
RiscVInstruction::Addi {
1616
dest: RiscVRegister::SP,
@@ -242,7 +242,7 @@ mod tests {
242242
fn test_loop() {
243243
let riscv_asm: Vec<RiscVInstruction> = vec![
244244
RiscVInstruction::Verbatim {
245-
text: START.to_string(),
245+
text: ARM_START.to_string(),
246246
},
247247
RiscVInstruction::Addi {
248248
dest: RiscVRegister::SP,

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