@@ -17,34 +17,38 @@ macro_rules! sorry {
1717pub fn translate ( riscv_instr : RiscVInstruction ) -> ArmInstruction {
1818 match riscv_instr {
1919 RiscVInstruction :: Addi { dest, src, imm } => {
20+ let width = RiscVWidth :: Word ;
2021 if imm >= 0 {
2122 ArmInstruction :: Add {
22- dest : map_register ( dest) ,
23- arg1 : map_register ( src) ,
23+ dest : map_register ( dest, width ) ,
24+ arg1 : map_register ( src, width ) ,
2425 arg2 : ArmVal :: Imm ( imm) ,
2526 }
2627 } else {
2728 ArmInstruction :: Sub {
28- dest : map_register ( dest) ,
29- arg1 : map_register ( src) ,
29+ dest : map_register ( dest, width ) ,
30+ arg1 : map_register ( src, width ) ,
3031 arg2 : ArmVal :: Imm ( imm) ,
3132 }
3233 }
3334 }
3435 RiscVInstruction :: S { width, src, dest } => ArmInstruction :: Str {
3536 width : map_width ( width) ,
36- src : map_register ( src) ,
37- dest : map_val ( dest) ,
37+ src : map_register ( src, width ) ,
38+ dest : map_val ( dest, width ) ,
3839 } ,
3940 RiscVInstruction :: L { width, dest, src } => ArmInstruction :: Ldr {
4041 width : map_width ( width) ,
41- dest : map_register ( dest) ,
42- src : map_val ( src) ,
42+ dest : map_register ( dest, width ) ,
43+ src : map_val ( src, width ) ,
4344 } ,
44- RiscVInstruction :: Mv { dest, src } => ArmInstruction :: Add {
45- dest : map_register ( dest) ,
46- arg1 : map_register ( src) ,
47- arg2 : ArmVal :: Imm ( 0 ) ,
45+ RiscVInstruction :: Mv { dest, src } => {
46+ let width = RiscVWidth :: Double ;
47+ ArmInstruction :: Add {
48+ dest : map_register ( dest, width) ,
49+ arg1 : map_register ( src, width) ,
50+ arg2 : ArmVal :: Imm ( 0 ) ,
51+ }
4852 } ,
4953 RiscVInstruction :: Add {
5054 width,
@@ -87,7 +91,7 @@ pub fn translate(riscv_instr: RiscVInstruction) -> ArmInstruction {
8791 }
8892
8993 ArmInstruction :: Add {
90- dest : map_register ( dest) ,
94+ dest : map_register ( dest, RiscVWidth :: Double ) ,
9195 arg1 : ArmRegister {
9296 width : ArmWidth :: Double ,
9397 name : ArmRegisterName :: Zero ,
@@ -111,11 +115,11 @@ fn map_register_name(riscv_reg: RiscVRegister) -> ArmRegisterName {
111115 ArmRegisterName :: A1
112116}
113117
114- fn map_val ( riscv_val : RiscVVal ) -> ArmVal {
118+ fn map_val ( riscv_val : RiscVVal , riscv_width : RiscVWidth ) -> ArmVal {
115119 match riscv_val {
116- RiscVVal :: RiscVRegister ( riscv_reg) => ArmVal :: Reg ( map_register ( riscv_reg) ) ,
120+ RiscVVal :: RiscVRegister ( riscv_reg) => ArmVal :: Reg ( map_register ( riscv_reg, riscv_width ) ) ,
117121 RiscVVal :: Immediate ( imm) => ArmVal :: Imm ( imm) ,
118- RiscVVal :: Offset { register, offset } => ArmVal :: RegOffset ( map_register ( register) , offset) ,
122+ RiscVVal :: Offset { register, offset } => ArmVal :: RegOffset ( map_register ( register, riscv_width ) , offset) ,
119123 }
120124}
121125
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