feat: Add support for single register access in GDB stub

Author: Satar07

edbgserver-cli/src/target.rs

@@ -230,7 +230,7 @@ impl MultiThreadBase for EdbgTarget {
         _tid: gdbstub::common::Tid,
     ) -> TargetResult<(), Self> {
         warn!("write_registers not fully implemented (requires ptrace or inline hooking)");
-        Ok(())
+        Err(TargetError::NonFatal)
     }
 
     fn read_addrs(
@@ -310,4 +310,13 @@ impl MultiThreadBase for EdbgTarget {
     fn support_resume(&mut self) -> Option<MultiThreadResumeOps<'_, Self>> {
         Some(self)
     }
+
+    #[inline(always)]
+    fn support_single_register_access(
+        &mut self,
+    ) -> Option<
+        gdbstub::target::ext::base::single_register_access::SingleRegisterAccessOps<'_, Tid, Self>,
+    > {
+        Some(self)
+    }
 }

edbgserver-cli/src/target/arch/aarch64.rs

@@ -4,7 +4,11 @@ use capstone::{
     prelude::*,
 };
 use edbgserver_common::DataT;
-use log::{debug, error};
+use gdbstub::{
+    common::Tid,
+    target::{TargetError, TargetResult, ext::base::single_register_access::SingleRegisterAccess},
+};
+use log::{debug, error, warn};
 
 use crate::target::EdbgTarget;
 
@@ -94,6 +98,53 @@ pub fn fill_regs(regs: &mut AArch64MinimalRegs, ctx: &DataT) {
     regs.cpsr = ctx.pstate as u32;
 }
 
+impl SingleRegisterAccess<Tid> for EdbgTarget {
+    fn read_register(
+        &mut self,
+        tid: Tid,
+        reg_id: <Self::Arch as gdbstub::arch::Arch>::RegId,
+        buf: &mut [u8],
+    ) -> TargetResult<usize, Self> {
+        let ctx = match &self.context {
+            Some(c) if !self.is_multi_thread || c.tid == tid.get() as u32 => c,
+            _ => {
+                warn!("read_register: no context with tid {}", tid.get());
+                return Ok(0);
+            }
+        };
+
+        match reg_id {
+            gdbstub_arch::aarch64::reg::id::AArch64RegId::X(n) => {
+                buf.copy_from_slice(&ctx.regs[n as usize].to_le_bytes());
+                Ok(8)
+            }
+            gdbstub_arch::aarch64::reg::id::AArch64RegId::Sp => {
+                buf.copy_from_slice(&ctx.sp.to_le_bytes());
+                Ok(8)
+            }
+            gdbstub_arch::aarch64::reg::id::AArch64RegId::Pc => {
+                buf.copy_from_slice(&ctx.pc.to_le_bytes());
+                Ok(8)
+            }
+            gdbstub_arch::aarch64::reg::id::AArch64RegId::Pstate => {
+                buf.copy_from_slice(&ctx.pstate.to_le_bytes());
+                Ok(8)
+            }
+            _ => Ok(0),
+        }
+    }
+
+    fn write_register(
+        &mut self,
+        _tid: Tid,
+        _reg_id: <Self::Arch as gdbstub::arch::Arch>::RegId,
+        _val: &[u8],
+    ) -> TargetResult<(), Self> {
+        warn!("write single register not fully implemented (requires ptrace or inline hooking)");
+        Err(TargetError::NonFatal)
+    }
+}
+
 impl EdbgTarget {
     fn create_capstone() -> Result<Capstone> {
         Capstone::new()

edbgserver-cli/src/target/arch/x86_64.rs

@@ -5,7 +5,14 @@ use capstone::{
     prelude::*,
 };
 use edbgserver_common::DataT;
-use gdbstub_arch::x86::reg::X86_64CoreRegs;
+use gdbstub::{
+    common::Tid,
+    target::{TargetError, TargetResult, ext::base::single_register_access::SingleRegisterAccess},
+};
+use gdbstub_arch::x86::reg::{
+    X86_64CoreRegs,
+    id::{X86_64CoreRegId, X86SegmentRegId},
+};
 use log::{debug, error, trace, warn};
 
 use crate::target::EdbgTarget;
@@ -32,6 +39,79 @@ pub fn fill_regs(regs: &mut X86_64CoreRegs, ctx: &DataT) {
     regs.eflags = ctx.eflags as u32;
 }
 
+impl SingleRegisterAccess<Tid> for EdbgTarget {
+    fn read_register(
+        &mut self,
+        tid: Tid,
+        reg_id: <Self::Arch as gdbstub::arch::Arch>::RegId,
+        buf: &mut [u8],
+    ) -> TargetResult<usize, Self> {
+        let ctx = match &self.context {
+            Some(c) if !self.is_multi_thread || c.tid == tid.get() as u32 => c,
+            _ => {
+                warn!("read_register: no context with tid {}", tid.get());
+                return Ok(0);
+            }
+        };
+
+        match reg_id {
+            X86_64CoreRegId::Gpr(i) => {
+                // RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, r8-r15
+                let val = match i {
+                    0 => ctx.rax,
+                    1 => ctx.rbx,
+                    2 => ctx.rcx,
+                    3 => ctx.rdx,
+                    4 => ctx.rsi,
+                    5 => ctx.rdi,
+                    6 => ctx.rbp,
+                    7 => ctx.rsp,
+                    8 => ctx.r8,
+                    9 => ctx.r9,
+                    10 => ctx.r10,
+                    11 => ctx.r11,
+                    12 => ctx.r12,
+                    13 => ctx.r13,
+                    14 => ctx.r14,
+                    15 => ctx.r15,
+                    _ => return Ok(0),
+                };
+                buf.copy_from_slice(&val.to_le_bytes());
+                Ok(8)
+            }
+            X86_64CoreRegId::Rip => {
+                buf.copy_from_slice(&ctx.rip.to_le_bytes());
+                Ok(8)
+            }
+            X86_64CoreRegId::Eflags => {
+                let val = ctx.eflags as u32;
+                buf.copy_from_slice(&val.to_le_bytes());
+                Ok(4)
+            }
+            X86_64CoreRegId::Segment(segments) => {
+                let val = match segments {
+                    X86SegmentRegId::CS => ctx.cs,
+                    X86SegmentRegId::SS => ctx.ss,
+                    _ => 0,
+                };
+                buf.copy_from_slice(&(val as u32).to_le_bytes());
+                Ok(4)
+            }
+            _ => Ok(0),
+        }
+    }
+
+    fn write_register(
+        &mut self,
+        _tid: Tid,
+        _reg_id: <Self::Arch as gdbstub::arch::Arch>::RegId,
+        _val: &[u8],
+    ) -> TargetResult<(), Self> {
+        warn!("write single register not fully implemented (requires ptrace or inline hooking)");
+        Err(TargetError::NonFatal)
+    }
+}
+
 impl EdbgTarget {
     fn create_capstone() -> Result<Capstone> {
         Capstone::new()