[AMD][AgentX] DSv4 FP4 MI355X agentX vLLM (#2109)

* fix: pin LMCache to commit 1720917e for DSv4 MI355X agentic vLLM

Pin LMCache to a specific commit to work around vLLM scheduler
ValueError with hybrid KV cache manager. Bump vLLM image to nightly,
tune LMCache config (blocking timeout, transfer mode), and narrow
sweep to lmcache conc=72 for focused debugging.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* chore: add perf-changelog entry for DSv4 MI355X agentic vLLM LMCache pin

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* fix: switch LMCache to dev branch for PR #3853 fix

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* fix: patch vLLM scheduler.py for hybrid KV cache and expand conc sweep

Apply vllm-project/vllm#45497 scheduler fix at runtime via gist to
resolve ValueError in _update_requests_with_invalid_blocks with hybrid
KV cache manager. Expand lmcache conc-list to [16, 32, 48, 64].

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* fix: increase LMCache mq_timeout from 600s to 6000s

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* chore: add DEP sweep and reduce dram-utilization for DSv4 MI355X agentic

Add DP-attention conc=[40,56,72] sweep, narrow lmcache to conc=[32,40],
and reduce dram-utilization from 0.80 to 0.60.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* chore: expand DEP sweep to high conc [100,150,200,250,300] for MI355X

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

* chore: reset DSv4 MI355X agentic sweep to baseline conc range

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

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Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
Co-authored-by: Cameron Quilici <cjquilici@gmail.com>

Author: 3 people