The AMDC hardware supports two encoder ports, but the FPGA has been configured for 1.
In the block diagram, the inputs are all going to one encoder block, with the second set being labeled as "alarm"
However, the "alarm" signals don't go anywhere.
Here, these are inputs into the top-level encoder (amdc_encoder_v1_0.v).
However, they are not propagated into the AXI file and are not used.
The FPGA should be updated to support both encoder ports.
The AMDC hardware supports two encoder ports, but the FPGA has been configured for 1.
In the block diagram, the inputs are all going to one encoder block, with the second set being labeled as "alarm"
However, the "alarm" signals don't go anywhere.
Here, these are inputs into the top-level encoder (
amdc_encoder_v1_0.v).However, they are not propagated into the AXI file and are not used.
The FPGA should be updated to support both encoder ports.