diff --git a/hw/amdc_revf.bd b/hw/amdc_revf.bd index 35a06aeb..0c657cb0 100644 --- a/hw/amdc_revf.bd +++ b/hw/amdc_revf.bd @@ -210,7 +210,12 @@ "xlconcat_2": "", "xlconstant_3": "", "amdc_eddy_current_se_0": "", - "amdc_amds_0": "" + "amdc_amds_0": "", + "xlconcat_0": "", + "xlconstant_1": "", + "xlslice_4": "", + "xlslice_5": "", + "NOT_gate_0": "" }, "xlconcat_0": "", "xlconstant_0": "", @@ -818,6 +823,18 @@ "direction": "I", "left": "15", "right": "0" + }, + "CAN0_TX": { + "direction": "O" + }, + "CAN0_RX": { + "direction": "I" + }, + "CAN1_RX": { + "direction": "I" + }, + "CAN1_TX": { + "direction": "O" } }, "components": { @@ -829,7 +846,7 @@ "value": "666.666687" }, "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { - "value": "10.000000" + "value": "100.000000" }, "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { "value": "10.158730" @@ -900,11 +917,29 @@ "PCW_APU_PERIPHERAL_FREQMHZ": { "value": "667" }, + "PCW_CAN0_CAN0_IO": { + "value": "EMIO" + }, + "PCW_CAN0_GRP_CLK_ENABLE": { + "value": "0" + }, "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN1_CAN1_IO": { + "value": "EMIO" + }, + "PCW_CAN1_GRP_CLK_ENABLE": { "value": "0" }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN_PERIPHERAL_FREQMHZ": { + "value": "100" + }, "PCW_CAN_PERIPHERAL_VALID": { - "value": "0" + "value": "1" }, "PCW_CLK0_FREQ": { "value": "200000000" @@ -970,7 +1005,10 @@ "value": "Share reset pin" }, "PCW_EN_CAN0": { - "value": "0" + "value": "1" + }, + "PCW_EN_CAN1": { + "value": "1" }, "PCW_EN_CLK0_PORT": { "value": "1" @@ -988,7 +1026,10 @@ "value": "1" }, "PCW_EN_EMIO_CAN0": { - "value": "0" + "value": "1" + }, + "PCW_EN_EMIO_CAN1": { + "value": "1" }, "PCW_EN_EMIO_CD_SDIO1": { "value": "1" @@ -1563,6 +1604,12 @@ "PCW_MIO_TREE_SIGNALS": { "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#rx#tx#mdc#mdio" }, + "PCW_P2F_CAN0_INTR": { + "value": "0" + }, + "PCW_P2F_CAN1_INTR": { + "value": "0" + }, "PCW_P2F_UART0_INTR": { "value": "1" }, @@ -2963,17 +3010,17 @@ } }, "interface_nets": { - "i04_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_i04_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "i04_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3269,17 +3316,17 @@ } }, "interface_nets": { - "m02_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m02_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m02_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3445,17 +3492,17 @@ } }, "interface_nets": { - "auto_pc_to_m04_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m04_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m04_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -3533,17 +3580,17 @@ } }, "interface_nets": { - "auto_pc_to_m05_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m05_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m05_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -3621,17 +3668,17 @@ } }, "interface_nets": { - "m06_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m06_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m06_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3709,17 +3756,17 @@ } }, "interface_nets": { - "m07_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m07_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m07_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3885,17 +3932,17 @@ } }, "interface_nets": { - "m09_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m09_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m09_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4027,17 +4074,17 @@ } }, "interface_nets": { - "m11_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m11_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m11_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4291,17 +4338,17 @@ } }, "interface_nets": { - "auto_pc_to_m14_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m14_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m14_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4697,17 +4744,17 @@ } }, "interface_nets": { - "auto_pc_to_m19_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m19_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m19_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4927,17 +4974,17 @@ } }, "interface_nets": { - "auto_pc_to_m22_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m22_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m22_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5333,17 +5380,17 @@ } }, "interface_nets": { - "auto_pc_to_m27_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m27_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m27_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5421,17 +5468,17 @@ } }, "interface_nets": { - "m28_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m28_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m28_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5509,17 +5556,17 @@ } }, "interface_nets": { - "auto_pc_to_m29_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m29_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m29_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5597,17 +5644,17 @@ } }, "interface_nets": { - "auto_pc_to_m30_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m30_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m30_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5685,17 +5732,17 @@ } }, "interface_nets": { - "auto_pc_to_m31_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m31_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m31_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -6039,70 +6086,124 @@ } }, "interface_nets": { - "m00_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "m08_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "M08_AXI", + "m08_couplers/M_AXI" ] }, - "ps7_0_axi_periph_to_s00_couplers": { + "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "tier2_xbar_0/M06_AXI", + "m06_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m00_couplers": { + "m07_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M00_AXI", - "m00_couplers/S_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, - "m01_couplers_to_ps7_0_axi_periph": { + "m09_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "M09_AXI", + "m09_couplers/M_AXI" ] }, - "m02_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m08_couplers": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "tier2_xbar_1/M00_AXI", + "m08_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m01_couplers": { + "tier2_xbar_1_to_m09_couplers": { "interface_ports": [ - "tier2_xbar_0/M01_AXI", - "m01_couplers/S_AXI" + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m02_couplers": { + "m10_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M02_AXI", - "m02_couplers/S_AXI" + "M10_AXI", + "m10_couplers/M_AXI" ] }, - "m03_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m10_couplers": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m03_couplers": { + "m11_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M03_AXI", - "m03_couplers/S_AXI" + "M11_AXI", + "m11_couplers/M_AXI" ] }, - "m04_couplers_to_ps7_0_axi_periph": { + "m12_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "M12_AXI", + "m12_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m11_couplers": { + "interface_ports": [ + "tier2_xbar_1/M03_AXI", + "m11_couplers/S_AXI" + ] + }, + "tier2_xbar_1_to_m12_couplers": { + "interface_ports": [ + "tier2_xbar_1/M04_AXI", + "m12_couplers/S_AXI" + ] + }, + "m13_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M13_AXI", + "m13_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m13_couplers": { + "interface_ports": [ + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" + ] + }, + "m14_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M14_AXI", + "m14_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m14_couplers": { + "interface_ports": [ + "tier2_xbar_1/M06_AXI", + "m14_couplers/S_AXI" + ] + }, + "m15_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M15_AXI", + "m15_couplers/M_AXI" + ] + }, + "tier2_xbar_0_to_m05_couplers": { + "interface_ports": [ + "tier2_xbar_0/M05_AXI", + "m05_couplers/S_AXI" + ] + }, + "m06_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M06_AXI", + "m06_couplers/M_AXI" ] }, "tier2_xbar_0_to_m04_couplers": { @@ -6117,136 +6218,220 @@ "m05_couplers/M_AXI" ] }, - "m06_couplers_to_ps7_0_axi_periph": { + "i04_couplers_to_tier2_xbar_4": { "interface_ports": [ - "M06_AXI", - "m06_couplers/M_AXI" + "i04_couplers/M_AXI", + "tier2_xbar_4/S00_AXI" ] }, - "tier2_xbar_0_to_m05_couplers": { + "xbar_to_i00_couplers": { "interface_ports": [ - "tier2_xbar_0/M05_AXI", - "m05_couplers/S_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "m07_couplers_to_ps7_0_axi_periph": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "tier2_xbar_0_to_m06_couplers": { + "xbar_to_i01_couplers": { "interface_ports": [ - "tier2_xbar_0/M06_AXI", - "m06_couplers/S_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m07_couplers": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "tier2_xbar_0/M07_AXI", - "m07_couplers/S_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "m08_couplers_to_ps7_0_axi_periph": { + "xbar_to_i02_couplers": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "xbar/M02_AXI", + "i02_couplers/S_AXI" ] }, - "m09_couplers_to_ps7_0_axi_periph": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, - "tier2_xbar_1_to_m08_couplers": { + "xbar_to_i03_couplers": { "interface_ports": [ - "tier2_xbar_1/M00_AXI", - "m08_couplers/S_AXI" + "xbar/M03_AXI", + "i03_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m09_couplers": { + "xbar_to_i04_couplers": { "interface_ports": [ - "tier2_xbar_1/M01_AXI", - "m09_couplers/S_AXI" + "xbar/M04_AXI", + "i04_couplers/S_AXI" ] }, - "m10_couplers_to_ps7_0_axi_periph": { + "i03_couplers_to_tier2_xbar_3": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "i03_couplers/M_AXI", + "tier2_xbar_3/S00_AXI" ] }, - "tier2_xbar_1_to_m10_couplers": { + "m37_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M02_AXI", - "m10_couplers/S_AXI" + "M37_AXI", + "m37_couplers/M_AXI" ] }, - "m11_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m37_couplers": { "interface_ports": [ - "M11_AXI", - "m11_couplers/M_AXI" + "tier2_xbar_4/M05_AXI", + "m37_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m11_couplers": { + "m34_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M03_AXI", - "m11_couplers/S_AXI" + "M34_AXI", + "m34_couplers/M_AXI" ] }, - "m12_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m33_couplers": { "interface_ports": [ - "M12_AXI", - "m12_couplers/M_AXI" + "tier2_xbar_4/M01_AXI", + "m33_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m24_couplers": { + "tier2_xbar_4_to_m34_couplers": { "interface_ports": [ - "tier2_xbar_3/M00_AXI", - "m24_couplers/S_AXI" + "tier2_xbar_4/M02_AXI", + "m34_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m12_couplers": { + "m35_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M04_AXI", - "m12_couplers/S_AXI" + "M35_AXI", + "m35_couplers/M_AXI" ] }, - "m13_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m35_couplers": { "interface_ports": [ - "M13_AXI", - "m13_couplers/M_AXI" + "tier2_xbar_4/M03_AXI", + "m35_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m13_couplers": { + "m36_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M05_AXI", - "m13_couplers/S_AXI" + "M36_AXI", + "m36_couplers/M_AXI" ] }, - "m14_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m36_couplers": { "interface_ports": [ - "M14_AXI", - "m14_couplers/M_AXI" + "tier2_xbar_4/M04_AXI", + "m36_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m14_couplers": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ - "tier2_xbar_1/M06_AXI", - "m14_couplers/S_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, - "m15_couplers_to_ps7_0_axi_periph": { + "m00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M15_AXI", - "m15_couplers/M_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m15_couplers": { + "s00_couplers_to_xbar": { "interface_ports": [ - "tier2_xbar_1/M07_AXI", - "m15_couplers/S_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "m01_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M01_AXI", + "m01_couplers/M_AXI" + ] + }, + "tier2_xbar_0_to_m00_couplers": { + "interface_ports": [ + "tier2_xbar_0/M00_AXI", + "m00_couplers/S_AXI" + ] + }, + "tier2_xbar_0_to_m03_couplers": { + "interface_ports": [ + "tier2_xbar_0/M03_AXI", + "m03_couplers/S_AXI" + ] + }, + "m04_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M04_AXI", + "m04_couplers/M_AXI" + ] + }, + "tier2_xbar_0_to_m01_couplers": { + "interface_ports": [ + "tier2_xbar_0/M01_AXI", + "m01_couplers/S_AXI" + ] + }, + "m02_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, + "tier2_xbar_0_to_m02_couplers": { + "interface_ports": [ + "tier2_xbar_0/M02_AXI", + "m02_couplers/S_AXI" + ] + }, + "m03_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M03_AXI", + "m03_couplers/M_AXI" + ] + }, + "tier2_xbar_3_to_m30_couplers": { + "interface_ports": [ + "tier2_xbar_3/M06_AXI", + "m30_couplers/S_AXI" + ] + }, + "m31_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M31_AXI", + "m31_couplers/M_AXI" + ] + }, + "tier2_xbar_3_to_m31_couplers": { + "interface_ports": [ + "tier2_xbar_3/M07_AXI", + "m31_couplers/S_AXI" + ] + }, + "m32_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M32_AXI", + "m32_couplers/M_AXI" + ] + }, + "m33_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M33_AXI", + "m33_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m32_couplers": { + "interface_ports": [ + "tier2_xbar_4/M00_AXI", + "m32_couplers/S_AXI" ] }, "m16_couplers_to_ps7_0_axi_periph": { @@ -6255,6 +6440,12 @@ "m16_couplers/M_AXI" ] }, + "tier2_xbar_1_to_m15_couplers": { + "interface_ports": [ + "tier2_xbar_1/M07_AXI", + "m15_couplers/S_AXI" + ] + }, "tier2_xbar_2_to_m16_couplers": { "interface_ports": [ "tier2_xbar_2/M00_AXI", @@ -6279,18 +6470,18 @@ "m18_couplers/M_AXI" ] }, - "m19_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M19_AXI", - "m19_couplers/M_AXI" - ] - }, "tier2_xbar_2_to_m18_couplers": { "interface_ports": [ "tier2_xbar_2/M02_AXI", "m18_couplers/S_AXI" ] }, + "m19_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M19_AXI", + "m19_couplers/M_AXI" + ] + }, "tier2_xbar_2_to_m19_couplers": { "interface_ports": [ "tier2_xbar_2/M03_AXI", @@ -6329,92 +6520,26 @@ }, "tier2_xbar_2_to_m22_couplers": { "interface_ports": [ - "tier2_xbar_2/M06_AXI", - "m22_couplers/S_AXI" - ] - }, - "m23_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M23_AXI", - "m23_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m23_couplers": { - "interface_ports": [ - "tier2_xbar_2/M07_AXI", - "m23_couplers/S_AXI" - ] - }, - "m24_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M24_AXI", - "m24_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m37_couplers": { - "interface_ports": [ - "tier2_xbar_4/M05_AXI", - "m37_couplers/S_AXI" - ] - }, - "xbar_to_i00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "i00_couplers/S_AXI" - ] - }, - "i00_couplers_to_tier2_xbar_0": { - "interface_ports": [ - "i00_couplers/M_AXI", - "tier2_xbar_0/S00_AXI" - ] - }, - "xbar_to_i01_couplers": { - "interface_ports": [ - "xbar/M01_AXI", - "i01_couplers/S_AXI" - ] - }, - "xbar_to_i02_couplers": { - "interface_ports": [ - "xbar/M02_AXI", - "i02_couplers/S_AXI" - ] - }, - "i01_couplers_to_tier2_xbar_1": { - "interface_ports": [ - "i01_couplers/M_AXI", - "tier2_xbar_1/S00_AXI" - ] - }, - "i02_couplers_to_tier2_xbar_2": { - "interface_ports": [ - "i02_couplers/M_AXI", - "tier2_xbar_2/S00_AXI" - ] - }, - "xbar_to_i03_couplers": { - "interface_ports": [ - "xbar/M03_AXI", - "i03_couplers/S_AXI" + "tier2_xbar_2/M06_AXI", + "m22_couplers/S_AXI" ] }, - "i03_couplers_to_tier2_xbar_3": { + "m23_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i03_couplers/M_AXI", - "tier2_xbar_3/S00_AXI" + "M23_AXI", + "m23_couplers/M_AXI" ] }, - "xbar_to_i04_couplers": { + "tier2_xbar_2_to_m23_couplers": { "interface_ports": [ - "xbar/M04_AXI", - "i04_couplers/S_AXI" + "tier2_xbar_2/M07_AXI", + "m23_couplers/S_AXI" ] }, - "i04_couplers_to_tier2_xbar_4": { + "m24_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i04_couplers/M_AXI", - "tier2_xbar_4/S00_AXI" + "M24_AXI", + "m24_couplers/M_AXI" ] }, "m25_couplers_to_ps7_0_axi_periph": { @@ -6423,10 +6548,10 @@ "m25_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m25_couplers": { + "tier2_xbar_3_to_m24_couplers": { "interface_ports": [ - "tier2_xbar_3/M01_AXI", - "m25_couplers/S_AXI" + "tier2_xbar_3/M00_AXI", + "m24_couplers/S_AXI" ] }, "m26_couplers_to_ps7_0_axi_periph": { @@ -6435,6 +6560,12 @@ "m26_couplers/M_AXI" ] }, + "tier2_xbar_3_to_m25_couplers": { + "interface_ports": [ + "tier2_xbar_3/M01_AXI", + "m25_couplers/S_AXI" + ] + }, "tier2_xbar_3_to_m26_couplers": { "interface_ports": [ "tier2_xbar_3/M02_AXI", @@ -6447,18 +6578,18 @@ "m27_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m27_couplers": { - "interface_ports": [ - "tier2_xbar_3/M03_AXI", - "m27_couplers/S_AXI" - ] - }, "m28_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M28_AXI", "m28_couplers/M_AXI" ] }, + "tier2_xbar_3_to_m27_couplers": { + "interface_ports": [ + "tier2_xbar_3/M03_AXI", + "m27_couplers/S_AXI" + ] + }, "tier2_xbar_3_to_m28_couplers": { "interface_ports": [ "tier2_xbar_3/M04_AXI", @@ -6482,90 +6613,6 @@ "M30_AXI", "m30_couplers/M_AXI" ] - }, - "m31_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M31_AXI", - "m31_couplers/M_AXI" - ] - }, - "tier2_xbar_3_to_m30_couplers": { - "interface_ports": [ - "tier2_xbar_3/M06_AXI", - "m30_couplers/S_AXI" - ] - }, - "tier2_xbar_3_to_m31_couplers": { - "interface_ports": [ - "tier2_xbar_3/M07_AXI", - "m31_couplers/S_AXI" - ] - }, - "m32_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M32_AXI", - "m32_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m32_couplers": { - "interface_ports": [ - "tier2_xbar_4/M00_AXI", - "m32_couplers/S_AXI" - ] - }, - "m33_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M33_AXI", - "m33_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m33_couplers": { - "interface_ports": [ - "tier2_xbar_4/M01_AXI", - "m33_couplers/S_AXI" - ] - }, - "m34_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M34_AXI", - "m34_couplers/M_AXI" - ] - }, - "m35_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M35_AXI", - "m35_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m34_couplers": { - "interface_ports": [ - "tier2_xbar_4/M02_AXI", - "m34_couplers/S_AXI" - ] - }, - "tier2_xbar_4_to_m35_couplers": { - "interface_ports": [ - "tier2_xbar_4/M03_AXI", - "m35_couplers/S_AXI" - ] - }, - "m36_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M36_AXI", - "m36_couplers/M_AXI" - ] - }, - "m37_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M37_AXI", - "m37_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m36_couplers": { - "interface_ports": [ - "tier2_xbar_4/M04_AXI", - "m36_couplers/S_AXI" - ] } }, "nets": { @@ -7161,28 +7208,28 @@ } }, "interface_nets": { - "Conn22": { + "ps7_0_axi_periph_M13_AXI": { "interface_ports": [ - "M22_AXI", - "ps7_0_axi_periph/M22_AXI" + "M13_AXI", + "ps7_0_axi_periph/M13_AXI" ] }, - "Conn28": { + "Conn27": { "interface_ports": [ - "M28_AXI", - "ps7_0_axi_periph/M28_AXI" + "M27_AXI", + "ps7_0_axi_periph/M27_AXI" ] }, - "Conn23": { + "Conn13": { "interface_ports": [ - "M23_AXI", - "ps7_0_axi_periph/M23_AXI" + "M12_AXI", + "ps7_0_axi_periph/M12_AXI" ] }, - "processing_system7_0_M_AXI_GP0": { + "Conn1": { "interface_ports": [ - "processing_system7_0/M_AXI_GP0", - "ps7_0_axi_periph/S00_AXI" + "M00_AXI", + "ps7_0_axi_periph/M00_AXI" ] }, "Conn6": { @@ -7191,76 +7238,76 @@ "ps7_0_axi_periph/M05_AXI" ] }, - "Conn29": { + "Conn17": { "interface_ports": [ - "M33_AXI", - "ps7_0_axi_periph/M33_AXI" + "M17_AXI", + "ps7_0_axi_periph/M17_AXI" ] }, - "Conn19": { + "Conn28": { "interface_ports": [ - "M19_AXI", - "ps7_0_axi_periph/M19_AXI" + "M28_AXI", + "ps7_0_axi_periph/M28_AXI" ] }, - "Conn9": { + "processing_system7_0_M_AXI_GP0": { "interface_ports": [ - "M08_AXI", - "ps7_0_axi_periph/M08_AXI" + "processing_system7_0/M_AXI_GP0", + "ps7_0_axi_periph/S00_AXI" ] }, - "Conn13": { + "Conn22": { "interface_ports": [ - "M12_AXI", - "ps7_0_axi_periph/M12_AXI" + "M22_AXI", + "ps7_0_axi_periph/M22_AXI" ] }, - "Conn16": { + "Conn23": { "interface_ports": [ - "M16_AXI", - "ps7_0_axi_periph/M16_AXI" + "M23_AXI", + "ps7_0_axi_periph/M23_AXI" ] }, - "Conn27": { + "Conn19": { "interface_ports": [ - "M27_AXI", - "ps7_0_axi_periph/M27_AXI" + "M19_AXI", + "ps7_0_axi_periph/M19_AXI" ] }, - "Conn15": { + "Conn9": { "interface_ports": [ - "M15_AXI", - "ps7_0_axi_periph/M15_AXI" + "M08_AXI", + "ps7_0_axi_periph/M08_AXI" ] }, - "Conn12": { + "Conn29": { "interface_ports": [ - "M11_AXI", - "ps7_0_axi_periph/M11_AXI" + "M33_AXI", + "ps7_0_axi_periph/M33_AXI" ] }, - "ps7_0_axi_periph_M36_AXI": { + "Conn15": { "interface_ports": [ - "M36_AXI", - "ps7_0_axi_periph/M36_AXI" + "M15_AXI", + "ps7_0_axi_periph/M15_AXI" ] }, - "ps7_0_axi_periph_M37_AXI": { + "Conn16": { "interface_ports": [ - "M37_AXI", - "ps7_0_axi_periph/M37_AXI" + "M16_AXI", + "ps7_0_axi_periph/M16_AXI" ] }, - "Conn17": { + "Conn12": { "interface_ports": [ - "M17_AXI", - "ps7_0_axi_periph/M17_AXI" + "M11_AXI", + "ps7_0_axi_periph/M11_AXI" ] }, - "Conn1": { + "ps7_0_axi_periph_M36_AXI": { "interface_ports": [ - "M00_AXI", - "ps7_0_axi_periph/M00_AXI" + "M36_AXI", + "ps7_0_axi_periph/M36_AXI" ] }, "processing_system7_0_DDR": { @@ -7275,16 +7322,10 @@ "ps7_0_axi_periph/M18_AXI" ] }, - "ps7_0_axi_periph_M32_AXI": { - "interface_ports": [ - "M32_AXI", - "ps7_0_axi_periph/M32_AXI" - ] - }, - "Conn10": { + "ps7_0_axi_periph_M37_AXI": { "interface_ports": [ - "M09_AXI", - "ps7_0_axi_periph/M09_AXI" + "M37_AXI", + "ps7_0_axi_periph/M37_AXI" ] }, "ps7_0_axi_periph_M30_AXI": { @@ -7293,28 +7334,34 @@ "ps7_0_axi_periph/M30_AXI" ] }, - "Conn21": { - "interface_ports": [ - "M21_AXI", - "ps7_0_axi_periph/M21_AXI" - ] - }, "Conn2": { "interface_ports": [ "M01_AXI", "ps7_0_axi_periph/M01_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "ps7_0_axi_periph_M32_AXI": { + "interface_ports": [ + "M32_AXI", + "ps7_0_axi_periph/M32_AXI" + ] + }, + "Conn10": { + "interface_ports": [ + "M09_AXI", + "ps7_0_axi_periph/M09_AXI" + ] + }, + "Conn11": { "interface_ports": [ - "FIXED_IO", - "processing_system7_0/FIXED_IO" + "M10_AXI", + "ps7_0_axi_periph/M10_AXI" ] }, - "Conn3": { + "Conn21": { "interface_ports": [ - "M02_AXI", - "ps7_0_axi_periph/M02_AXI" + "M21_AXI", + "ps7_0_axi_periph/M21_AXI" ] }, "Conn8": { @@ -7323,16 +7370,16 @@ "ps7_0_axi_periph/M07_AXI" ] }, - "Conn14": { + "Conn3": { "interface_ports": [ - "M14_AXI", - "ps7_0_axi_periph/M14_AXI" + "M02_AXI", + "ps7_0_axi_periph/M02_AXI" ] }, - "Conn11": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "M10_AXI", - "ps7_0_axi_periph/M10_AXI" + "FIXED_IO", + "processing_system7_0/FIXED_IO" ] }, "Conn25": { @@ -7341,34 +7388,22 @@ "ps7_0_axi_periph/M25_AXI" ] }, - "ps7_0_axi_periph_M13_AXI": { - "interface_ports": [ - "M13_AXI", - "ps7_0_axi_periph/M13_AXI" - ] - }, "Conn20": { "interface_ports": [ "M20_AXI", "ps7_0_axi_periph/M20_AXI" ] }, - "Conn24": { - "interface_ports": [ - "M24_AXI", - "ps7_0_axi_periph/M24_AXI" - ] - }, "Conn7": { "interface_ports": [ "M06_AXI", "ps7_0_axi_periph/M06_AXI" ] }, - "Conn26": { + "Conn14": { "interface_ports": [ - "M26_AXI", - "ps7_0_axi_periph/M26_AXI" + "M14_AXI", + "ps7_0_axi_periph/M14_AXI" ] }, "Conn5": { @@ -7377,10 +7412,16 @@ "ps7_0_axi_periph/M04_AXI" ] }, - "Conn4": { + "Conn24": { "interface_ports": [ - "M03_AXI", - "ps7_0_axi_periph/M03_AXI" + "M24_AXI", + "ps7_0_axi_periph/M24_AXI" + ] + }, + "Conn26": { + "interface_ports": [ + "M26_AXI", + "ps7_0_axi_periph/M26_AXI" ] }, "ps7_0_axi_periph_M29_AXI": { @@ -7389,6 +7430,12 @@ "ps7_0_axi_periph/M29_AXI" ] }, + "Conn4": { + "interface_ports": [ + "M03_AXI", + "ps7_0_axi_periph/M03_AXI" + ] + }, "ps7_0_axi_periph_M31_AXI": { "interface_ports": [ "M31_AXI", @@ -7519,6 +7566,30 @@ "IRQ_F2P", "processing_system7_0/IRQ_F2P" ] + }, + "processing_system7_0_CAN0_PHY_TX": { + "ports": [ + "processing_system7_0/CAN0_PHY_TX", + "CAN0_TX" + ] + }, + "processing_system7_0_CAN1_PHY_TX": { + "ports": [ + "processing_system7_0/CAN1_PHY_TX", + "CAN1_TX" + ] + }, + "CAN0_RX_1": { + "ports": [ + "CAN0_RX", + "processing_system7_0/CAN0_PHY_RX" + ] + }, + "CAN1_RX_1": { + "ports": [ + "CAN1_RX", + "processing_system7_0/CAN1_PHY_RX" + ] } } }, @@ -7648,18 +7719,18 @@ } }, "interface_nets": { - "Conn1": { - "interface_ports": [ - "S00_AXI2", - "amdc_inv_status_mux_0/S00_AXI" - ] - }, "ps7_0_axi_periph_M02_AXI": { "interface_ports": [ "S00_AXI", "amdc_inverters_0/S00_AXI" ] }, + "Conn1": { + "interface_ports": [ + "S00_AXI2", + "amdc_inv_status_mux_0/S00_AXI" + ] + }, "ps7_0_axi_periph_M06_AXI": { "interface_ports": [ "S00_AXI1", @@ -8187,24 +8258,6 @@ } }, "interface_nets": { - "S00_AXI6_1": { - "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" - ] - }, - "hier_ps_M48_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" - ] - }, - "S00_AXI4_1": { - "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" - ] - }, "S00_AXI1_1": { "interface_ports": [ "S00_AXI1", @@ -8217,11 +8270,29 @@ "hier_ild1420_0/S00_AXI" ] }, + "hier_ps_M48_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" + ] + }, + "S00_AXI6_1": { + "interface_ports": [ + "S00_AXI6", + "amdc_amds_0/S00_AXI" + ] + }, "S00_AXI5_1": { "interface_ports": [ "S00_AXI5", "amdc_gpio_direct_0/S00_AXI" ] + }, + "S00_AXI4_1": { + "interface_ports": [ + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" + ] } }, "nets": { @@ -8261,10 +8332,10 @@ "ports": [ "xlconstant_0/dout", "amdc_gp3io_mux_0/device3_out", - "amdc_gp3io_mux_0/device5_out", "amdc_gp3io_mux_0/device6_out", "amdc_gp3io_mux_0/device7_out", - "amdc_gp3io_mux_0/device8_out" + "amdc_gp3io_mux_0/device8_out", + "amdc_gp3io_mux_0/device5_out" ] }, "amdc_eddy_current_se_0_sensor_control_out": { @@ -8716,6 +8787,18 @@ "amdc_gpio_direct_0/S00_AXI" ] }, + "S00_AXI3_1": { + "interface_ports": [ + "S00_AXI3", + "hier_ild1420_0/S00_AXI" + ] + }, + "S00_AXI4_1": { + "interface_ports": [ + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" + ] + }, "hier_ps_M48_AXI": { "interface_ports": [ "S00_AXI", @@ -8733,18 +8816,6 @@ "S00_AXI1", "amdc_eddy_current_se_0/S00_AXI" ] - }, - "S00_AXI3_1": { - "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" - ] - }, - "S00_AXI4_1": { - "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" - ] } }, "nets": { @@ -9233,10 +9304,10 @@ } }, "interface_nets": { - "S00_AXI1_1": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] }, "S00_AXI5_1": { @@ -9245,16 +9316,16 @@ "amdc_gpio_direct_0/S00_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI1_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" ] }, - "S00_AXI6_1": { + "hier_ps_M48_AXI": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -9263,10 +9334,10 @@ "hier_ild1420_0/S00_AXI1" ] }, - "hier_ps_M48_AXI": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] } }, @@ -9496,6 +9567,22 @@ }, "amds_done": { "direction": "O" + }, + "CAN0_TX": { + "direction": "I" + }, + "CAN1_TX": { + "direction": "I" + }, + "CAN0_RX": { + "direction": "O", + "left": "0", + "right": "0" + }, + "CAN1_RX": { + "direction": "O", + "left": "0", + "right": "0" } }, "components": { @@ -9572,17 +9659,17 @@ } }, "interface_nets": { - "hier_ps_M13_AXI": { - "interface_ports": [ - "S00_AXI1", - "amdc_ild1420_1/S00_AXI" - ] - }, "hier_ps_M12_AXI": { "interface_ports": [ "S00_AXI", "amdc_ild1420_0/S00_AXI" ] + }, + "hier_ps_M13_AXI": { + "interface_ports": [ + "S00_AXI1", + "amdc_ild1420_1/S00_AXI" + ] } }, "nets": { @@ -9753,25 +9840,96 @@ "amdc_amds_0": { "vlnv": "xilinx.com:user:amdc_amds:1.0", "xci_name": "amdc_revf_amdc_amds_0_3" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "amdc_revf_xlconcat_0_2", + "parameters": { + "NUM_PORTS": { + "value": "3" + } + } + }, + "xlconstant_1": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "amdc_revf_xlconstant_1_1", + "parameters": { + "CONST_VAL": { + "value": "0" + } + } + }, + "xlslice_4": { + "vlnv": "xilinx.com:ip:xlslice:1.0", + "xci_name": "amdc_revf_xlslice_4_2", + "parameters": { + "DIN_FROM": { + "value": "1" + }, + "DIN_TO": { + "value": "1" + }, + "DIN_WIDTH": { + "value": "3" + }, + "DOUT_WIDTH": { + "value": "1" + } + } + }, + "xlslice_5": { + "vlnv": "xilinx.com:ip:xlslice:1.0", + "xci_name": "amdc_revf_xlslice_5_0", + "parameters": { + "DIN_FROM": { + "value": "0" + }, + "DIN_TO": { + "value": "0" + }, + "DIN_WIDTH": { + "value": "3" + }, + "DOUT_WIDTH": { + "value": "1" + } + } + }, + "NOT_gate_0": { + "vlnv": "xilinx.com:module_ref:NOT_gate:1.0", + "xci_name": "amdc_revf_NOT_gate_0_2", + "reference_info": { + "ref_type": "hdl", + "ref_name": "NOT_gate", + "boundary_crc": "0x0" + }, + "ports": { + "a": { + "direction": "I" + }, + "b": { + "direction": "O" + } + } } }, "interface_nets": { - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, "S00_AXI6_1": { "interface_ports": [ "S00_AXI6", "amdc_amds_0/S00_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI4_1": { + "interface_ports": [ + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" + ] + }, + "S00_AXI1_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" ] }, "hier_ps_M48_AXI": { @@ -9780,16 +9938,16 @@ "amdc_gp3io_mux_0/S00_AXI" ] }, - "S00_AXI4_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, - "S00_AXI1_1": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] } }, @@ -9830,7 +9988,6 @@ "ports": [ "xlconstant_0/dout", "amdc_gp3io_mux_0/device3_out", - "amdc_gp3io_mux_0/device5_out", "amdc_gp3io_mux_0/device6_out", "amdc_gp3io_mux_0/device7_out", "amdc_gp3io_mux_0/device8_out" @@ -9956,6 +10113,55 @@ "amdc_amds_0/sync_adc", "xlconcat_2/In0" ] + }, + "CAN0_TX_1": { + "ports": [ + "CAN0_TX", + "xlconcat_0/In0" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "amdc_gp3io_mux_0/device5_out" + ] + }, + "amdc_gp3io_mux_0_device5_in": { + "ports": [ + "amdc_gp3io_mux_0/device5_in", + "xlslice_4/Din", + "xlslice_5/Din" + ] + }, + "NOT_gate_0_b": { + "ports": [ + "NOT_gate_0/b", + "CAN0_RX" + ] + }, + "xlslice_4_Dout": { + "ports": [ + "xlslice_4/Dout", + "NOT_gate_0/a" + ] + }, + "xlslice_5_Dout": { + "ports": [ + "xlslice_5/Dout", + "CAN1_RX" + ] + }, + "CAN1_TX_1": { + "ports": [ + "CAN1_TX", + "xlconcat_0/In1" + ] + }, + "xlconstant_1_dout": { + "ports": [ + "xlconstant_1/dout", + "xlconcat_0/In2" + ] } } }, @@ -9994,46 +10200,28 @@ } }, "interface_nets": { - "hier_ps_M31_AXI": { - "interface_ports": [ - "hier_ps/M31_AXI", - "hier_gpio_2/S00_AXI5" - ] - }, - "S00_AXI1_5": { - "interface_ports": [ - "hier_gpio_3/S00_AXI1", - "hier_ps/M26_AXI" - ] - }, "hier_ps_M37_AXI1": { "interface_ports": [ "hier_ps/M37_AXI", "hier_gpio_3/S00_AXI6" ] }, - "S00_AXI3_3": { - "interface_ports": [ - "hier_gpio_2/S00_AXI3", - "hier_ps/M22_AXI" - ] - }, - "hier_ps_M37_AXI": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "amdc_dac_0/S00_AXI", - "hier_ps/M05_AXI" + "FIXED_IO", + "hier_ps/FIXED_IO" ] }, - "S00_AXI3_2": { + "S00_AXI_1": { "interface_ports": [ - "hier_gpio_1/S00_AXI3", - "hier_ps/M17_AXI" + "hier_powerstack/S00_AXI", + "hier_ps/M06_AXI" ] }, - "hier_ps_M34_AXI": { + "hier_ps_M33_AXI1": { "interface_ports": [ - "amdc_encoder_0/S00_AXI", - "hier_ps/M02_AXI" + "amdc_timing_manager_0/S00_AXI", + "hier_ps/M33_AXI" ] }, "processing_system7_0_DDR": { @@ -10042,100 +10230,100 @@ "hier_ps/DDR" ] }, - "hier_ps_M36_AXI1": { + "hier_ps_M35_AXI": { "interface_ports": [ - "hier_ps/M36_AXI", - "hier_gpio_1/S00_AXI6" + "amdc_leds_0/S00_AXI", + "hier_ps/M03_AXI" ] }, - "hier_ps_M30_AXI": { + "S00_AXI_2": { "interface_ports": [ - "hier_ps/M30_AXI", - "hier_gpio_1/S00_AXI5" + "hier_gpio_0/S00_AXI", + "hier_ps/M09_AXI" ] }, - "S00_AXI1_3": { + "hier_ps_M31_AXI": { "interface_ports": [ - "hier_gpio_1/S00_AXI1", - "hier_ps/M16_AXI" + "hier_ps/M31_AXI", + "hier_gpio_2/S00_AXI5" ] }, - "S00_AXI1_1": { + "hier_ps_M36_AXI": { "interface_ports": [ - "hier_powerstack/S00_AXI1", - "hier_ps/M07_AXI" + "amdc_adc_0/S00_AXI", + "hier_ps/M04_AXI" ] }, - "S00_AXI4_4": { + "S00_AXI_3": { "interface_ports": [ - "hier_gpio_3/S00_AXI4", - "hier_ps/M28_AXI" + "hier_gpio_1/S00_AXI", + "hier_ps/M14_AXI" ] }, - "S00_AXI1_4": { + "S00_AXI2_1": { "interface_ports": [ - "hier_gpio_2/S00_AXI1", - "hier_ps/M21_AXI" + "hier_powerstack/S00_AXI2", + "hier_ps/M08_AXI" ] }, - "hier_ps_M35_AXI1": { + "S00_AXI_5": { "interface_ports": [ - "hier_ps/M35_AXI", - "hier_gpio_0/S00_AXI6" + "hier_gpio_3/S00_AXI", + "hier_ps/M24_AXI" ] }, - "S00_AXI4_2": { + "hier_ps_M29_AXI": { "interface_ports": [ - "hier_gpio_1/S00_AXI4", - "hier_ps/M18_AXI" + "hier_ps/M29_AXI", + "hier_gpio_0/S00_AXI5" ] }, - "S00_AXI3_4": { + "hier_ps_M32_AXI1": { "interface_ports": [ - "hier_gpio_3/S00_AXI3", - "hier_ps/M27_AXI" + "hier_ps/M32_AXI", + "hier_gpio_3/S00_AXI5" ] }, - "S00_AXI3_1": { + "S00_AXI_4": { "interface_ports": [ - "hier_gpio_0/S00_AXI3", - "hier_ps/M12_AXI" + "hier_gpio_2/S00_AXI", + "hier_ps/M19_AXI" ] }, - "hier_ps_M35_AXI": { + "hier_ps_M30_AXI": { "interface_ports": [ - "amdc_leds_0/S00_AXI", - "hier_ps/M03_AXI" + "hier_ps/M30_AXI", + "hier_gpio_1/S00_AXI5" ] }, - "hier_ps_M33_AXI1": { + "S00_AXI3_4": { "interface_ports": [ - "amdc_timing_manager_0/S00_AXI", - "hier_ps/M33_AXI" + "hier_gpio_3/S00_AXI3", + "hier_ps/M27_AXI" ] }, - "S00_AXI_1": { + "S00_AXI4_2": { "interface_ports": [ - "hier_powerstack/S00_AXI", - "hier_ps/M06_AXI" + "hier_gpio_1/S00_AXI4", + "hier_ps/M18_AXI" ] }, - "S00_AXI_5": { + "S00_AXI3_2": { "interface_ports": [ - "hier_gpio_3/S00_AXI", - "hier_ps/M24_AXI" + "hier_gpio_1/S00_AXI3", + "hier_ps/M17_AXI" ] }, - "hier_ps_M29_AXI": { + "S00_AXI4_1": { "interface_ports": [ - "hier_ps/M29_AXI", - "hier_gpio_0/S00_AXI5" + "hier_gpio_0/S00_AXI4", + "hier_ps/M13_AXI" ] }, - "S00_AXI_3": { + "S00_AXI1_4": { "interface_ports": [ - "hier_gpio_1/S00_AXI", - "hier_ps/M14_AXI" + "hier_gpio_2/S00_AXI1", + "hier_ps/M21_AXI" ] }, "S00_AXI1_2": { @@ -10144,34 +10332,46 @@ "hier_ps/M11_AXI" ] }, - "hier_ps_M34_AXI1": { + "hier_ps_M35_AXI1": { "interface_ports": [ - "hier_ps/M34_AXI", - "hier_gpio_2/S00_AXI6" + "hier_ps/M35_AXI", + "hier_gpio_0/S00_AXI6" ] }, - "S00_AXI_4": { + "S00_AXI1_3": { "interface_ports": [ - "hier_gpio_2/S00_AXI", - "hier_ps/M19_AXI" + "hier_gpio_1/S00_AXI1", + "hier_ps/M16_AXI" ] }, - "S00_AXI4_1": { + "hier_ps_M34_AXI": { "interface_ports": [ - "hier_gpio_0/S00_AXI4", - "hier_ps/M13_AXI" + "amdc_encoder_0/S00_AXI", + "hier_ps/M02_AXI" ] }, - "hier_ps_M32_AXI1": { + "S00_AXI4_4": { "interface_ports": [ - "hier_ps/M32_AXI", - "hier_gpio_3/S00_AXI5" + "hier_gpio_3/S00_AXI4", + "hier_ps/M28_AXI" ] }, - "hier_ps_M36_AXI": { + "S00_AXI3_1": { "interface_ports": [ - "amdc_adc_0/S00_AXI", - "hier_ps/M04_AXI" + "hier_gpio_0/S00_AXI3", + "hier_ps/M12_AXI" + ] + }, + "S00_AXI3_3": { + "interface_ports": [ + "hier_gpio_2/S00_AXI3", + "hier_ps/M22_AXI" + ] + }, + "hier_ps_M36_AXI1": { + "interface_ports": [ + "hier_ps/M36_AXI", + "hier_gpio_1/S00_AXI6" ] }, "S00_AXI4_3": { @@ -10180,22 +10380,28 @@ "hier_ps/M23_AXI" ] }, - "S00_AXI2_1": { + "hier_ps_M37_AXI": { "interface_ports": [ - "hier_powerstack/S00_AXI2", - "hier_ps/M08_AXI" + "amdc_dac_0/S00_AXI", + "hier_ps/M05_AXI" ] }, - "S00_AXI_2": { + "S00_AXI1_1": { "interface_ports": [ - "hier_gpio_0/S00_AXI", - "hier_ps/M09_AXI" + "hier_powerstack/S00_AXI1", + "hier_ps/M07_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "S00_AXI1_5": { "interface_ports": [ - "FIXED_IO", - "hier_ps/FIXED_IO" + "hier_gpio_3/S00_AXI1", + "hier_ps/M26_AXI" + ] + }, + "hier_ps_M34_AXI1": { + "interface_ports": [ + "hier_ps/M34_AXI", + "hier_gpio_2/S00_AXI6" ] } }, @@ -10595,6 +10801,30 @@ "xlconcat_0/dout", "hier_ps/IRQ_F2P" ] + }, + "hier_ps_CAN0_tx": { + "ports": [ + "hier_ps/CAN0_TX", + "hier_gpio_3/CAN0_TX" + ] + }, + "hier_ps_CAN1_TX": { + "ports": [ + "hier_ps/CAN1_TX", + "hier_gpio_3/CAN1_TX" + ] + }, + "hier_gpio_3_CAN0_RX": { + "ports": [ + "hier_gpio_3/CAN0_RX", + "hier_ps/CAN0_RX" + ] + }, + "hier_gpio_3_CAN1_RX": { + "ports": [ + "hier_gpio_3/CAN1_RX", + "hier_ps/CAN1_RX" + ] } }, "comments": { diff --git a/sdk/app_cpu1/common/drv/can.c b/sdk/app_cpu1/common/drv/can.c new file mode 100644 index 00000000..1c0e73b0 --- /dev/null +++ b/sdk/app_cpu1/common/drv/can.c @@ -0,0 +1,430 @@ +#include "can.h" +#include "drv/uart.h" +#include "gp3io_mux.h" +#include "sys/defines.h" +#include "xcanps.h" +#include "xparameters.h" +#include + +#define CAN0_DEVICE_ID XPAR_XCANPS_0_DEVICE_ID +#define CAN1_DEVICE_ID XPAR_XCANPS_1_DEVICE_ID + +// Maximum CAN frame length in words. +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS (XCANPS_MAX_FRAME_SIZE / sizeof(u32)) + +// Default number of bytes of data sending +#define FRAME_DATA_LENGTH 8 + +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +// Two CAN peripherals +static XCanPs CanPs0; +static XCanPs CanPs1; + +// Representing device we are currently on +static XCanPs *CanPs; + +// Set the mode of the CAN device +int can_setmode(can_mode_t mode, can_peripheral_t device) +{ + printf("gggg\n"); + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + uint32_t currMode = XCanPs_GetMode(CanInstPtr); + printf("ffff\n"); + if (currMode == XCANPS_MODE_LOOPBACK && mode != CAN_CONFIG) { +#ifdef CAN_DEBUG + print("\nCAN peripheral currently in loopback mode. Can only enter config mode from here."); +#endif + return FAILURE; + } else if (currMode == XCANPS_MODE_NORMAL && mode != CAN_SLEEP && mode != CAN_CONFIG) { +#ifdef CAN_DEBUG + print("\nCAN peripheral currently in normal mode. Can only enter config or sleep mode from here."); +#endif + return FAILURE; + } + + printf("exit\n"); + XCanPs_EnterMode(CanInstPtr, mode); + +// // Wait to reach specified mode, should happen instantaneously +// while (XCanPs_GetMode(CanInstPtr) != mode) + ; + return SUCCESS; +} + +// Set Baud Rate Prescalar Register (BRPR) +int can_setbaud(int rate, can_peripheral_t device) +{ + int Status; + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + // Ensure CAN peripheral in config mode + if (XCanPs_GetMode(CanInstPtr) != XCANPS_MODE_CONFIG) { +#ifdef CAN_DEBUG + print("\nMust be in config mode to set baud rate prescalar register"); +#endif + return FAILURE; + } + + Status = XCanPs_SetBaudRatePrescaler(CanInstPtr, rate); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Set Bit Timing Register (BTR) +int can_set_btr(uint8_t sjw, uint8_t ts2, uint8_t ts1, can_peripheral_t device) +{ + int Status; + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + // Ensure CAN peripheral in config mode + if (XCanPs_GetMode(CanInstPtr) != XCANPS_MODE_CONFIG) { +#ifdef CAN_DEBUG + print("\nMust be in config mode to set bit timing register"); +#endif + return FAILURE; + } + + Status = XCanPs_SetBitTiming(CanInstPtr, sjw, ts2, ts1); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Set CAN peripheral that we are using currently +//int can_set_peripheral(int device_id, can_peripheral_t device) +//{ +// if (device_id != 1 && device_id != 0) +// return FAILURE; +// else if (device_id) +// CanPs = &CanPs1; +// else +// CanPs = &CanPs0; +// return SUCCESS; +//} + +// Initialize the CAN device, default settings +int can_init(int device_id) +{ + can_peripheral_t device; + XCanPs *CanInstPtr; + u16 DeviceId; + + // Initialize the user specified CAN peripheral + if (device_id != 1 && device_id != 0) { +#ifdef CAN_DEBUG + printf("device_id can only be 0 or 1\n"); +#endif + return FAILURE; + } else if (!device_id) { + DeviceId = CAN0_DEVICE_ID; + device = CAN0; + CanInstPtr = &CanPs0; + CanPs = &CanPs0; + printf("CAN0:\tInitializing...\n"); + } else { + DeviceId = CAN1_DEVICE_ID; + device = CAN1; + CanInstPtr = &CanPs1; + CanPs = &CanPs1; + printf("CAN1:\tInitializing...\n"); + } + + int Status; + XCanPs_Config *Config; + + // Initialize the CAN driver so that it's ready to use + // Look up the configuration in the config table, then initialize it + Config = XCanPs_LookupConfig(DeviceId); + if (Config == NULL || CanInstPtr == NULL) { + return FAILURE; + } + + Status = XCanPs_CfgInitialize(CanInstPtr, Config, Config->BaseAddr); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Run self-test on the device, which verifies basic sanity of the + // device and the driver + Status = XCanPs_SelfTest(CanInstPtr); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Enter Configuration Mode so that we can setup Baud Rate Precalar + // Register (BRPR) and Bit Timing Register (BTR). + Status = can_setmode(XCANPS_MODE_CONFIG, device); + if (Status != SUCCESS) + return FAILURE; + + // Set Baud Rate Prescalar Register (BRPR) and + // Bit Timing Register (BTR) + Status = can_setbaud(DEFAULT_BAUD_PRESCALAR, device); + if (Status != SUCCESS) { + return FAILURE; + } + Status = can_set_btr(DEFAULT_BTR_SYNCJUMPWIDTH, DEFAULT_BTR_SECOND_TIMESEGMENT, DEFAULT_BTR_FIRST_TIMESEGMENT, device); + + if (Status != SUCCESS) { + return FAILURE; + } + + printf("rrrr\n"); + + // Enter Normal Mode to use CAN peripheral + return can_setmode(XCANPS_MODE_NORMAL, device); +} + +int can_deinit() { + XCanPs *CanInstPtr = &CanPs0; + XCanPs_Reset(CanInstPtr); + CanInstPtr = &CanPs1; + XCanPs_Reset(CanInstPtr); + return SUCCESS; +} + +// Send a CAN packet +int can_send(can_packet_t packet, uint32_t num_bytes, can_peripheral_t device) +{ + u8 *FramePtr; + int i; + int Status; + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + packet.message_id = 1; + packet.num_bytes = num_bytes; + printf("\nID: %d", packet.message_id); + printf("\nNum Bytes:%d\n", packet.num_bytes); + for (i = 0; i < 8; i++) { + printf("%u ", packet.buffer[i]); + } + printf("\n"); + + // Check number of bytes user is sending at once is between 1 to 8 + if (num_bytes <= 0 || num_bytes > 8) { +#ifdef CAN_DEBUG + printf("Can only send 8 bytes at once!\n"); +#endif + return FAILURE; + } + + // Populate correct values for Identifier - check Zync 700 Reference Manual for meaning of this info + TxFrame[0] = (u32) XCanPs_CreateIdValue((u32) packet.message_id, 0, 0, 0, 0); + + // Specify number of bytes of data sending + TxFrame[1] = (u32) XCanPs_CreateDlcValue((u32) packet.num_bytes); + + // Populate the TX FIFO with CAN packet to send + FramePtr = (u8 *) (&TxFrame[2]); + for (i = 0; i < packet.num_bytes; i++) { + *FramePtr = (u8) packet.buffer[i]; + FramePtr++; + } + + // Check if TxFIFO is full + if (XCanPs_IsTxFifoFull(CanInstPtr) == TRUE) { +#ifdef CAN_DEBUG + printf("CAN TxFIFO is full, try sending your data again in a bit!\n"); +#endif + return FAILURE; + } + + // Send the frame + Status = XCanPs_Send(CanInstPtr, TxFrame); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Print latest can packet received +int can_rcv(uint8_t buffer[8], can_peripheral_t device) +{ + u8 *FramePtr; + int Status; + int i; + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + // Check if a frame is empty + if (XCanPs_IsRxEmpty(CanInstPtr) == TRUE) { +#ifdef CAN_DEBUG + printf("Currently there isn't a packet in the RxFIFO, try again in a bit!\n"); +#endif + return FAILURE; + } + + // Receive a frame and verify its contents + Status = XCanPs_Recv(CanInstPtr, RxFrame); + can_packet_t packet; + for (i = 0; i < 8; i++) { + packet.buffer[i] = 0; + } + if (Status == XST_SUCCESS) { + packet.message_id = (int) (RxFrame[0] >> 21); + packet.num_bytes = (int) (RxFrame[1] >> 28); + FramePtr = (u8 *) (&RxFrame[2]); + for (i = 0; i < packet.num_bytes; i++) { + packet.buffer[i] = *FramePtr; + buffer[i] = packet.buffer[i]; + FramePtr++; + } + return SUCCESS; + } + return FAILURE; +} + +// Print mode the CAN peripheral is in, useful for debugging purposes +void can_print_mode(can_peripheral_t device) +{ +#ifdef CAN_DEBUG + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + uint32_t mode; + mode = XCanPs_GetMode(CanInstPtr); + if (mode == XCANPS_MODE_NORMAL) + print("\nXCANPS_MODE_NORMAL"); + else if (mode == XCANPS_MODE_LOOPBACK) + print("\nXCANPS_MODE_LOOPBACK"); + else if (mode == XCANPS_MODE_CONFIG) + print("\nXCANPS_MODE_CONFIG"); + else if (mode == XCANPS_MODE_SLEEP) + print("\nXCANPS_MODE_SLEEP"); + else + print("\nOther mode"); +#endif +} + +// Print the CAN peripheral the user has set, useful for debugging purposes +void can_print_peripheral() +{ +#ifdef CAN_DEBUG + if (CanPs == &CanPs0) + print("\nCAN 0"); + else if (CanPs == &CanPs1) + print("\nCAN 1"); + else + print("\nCAN peripheral not set properly"); +#endif +} + +// Check packet received in loopback mode is correct +static int can_checkpacket(can_peripheral_t device) +{ + u8 *FramePtr; + int Status; + int Index; + + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + + // Wait until a frame is received + while (XCanPs_IsRxEmpty(CanInstPtr) == TRUE) + ; + + // Receive a frame and verify its contents + Status = XCanPs_Recv(CanInstPtr, RxFrame); + if (Status == XST_SUCCESS) { + // Verify Identifier and Data Length Code + if (RxFrame[0] != (u32) XCanPs_CreateIdValue((u32) DEFAULT_CAN_MESSAGE_ID, 0, 0, 0, 0)) + return XST_LOOPBACK_ERROR; + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) + return XST_LOOPBACK_ERROR; + + // Verify Data field contents + FramePtr = (u8 *) (&RxFrame[2]); + for (Index = 0; Index < FRAME_DATA_LENGTH; Index++) { + if (*FramePtr++ != (u8) Index) { + return XST_LOOPBACK_ERROR; + } + } + } + + return Status; +} + +// Run a sanity check loopback test +int can_loopback_test(can_peripheral_t device) +{ + + int Status; + uint8_t data[FRAME_DATA_LENGTH]; + + // Check we are in loopback mode + uint32_t mode; + XCanPs *CanInstPtr; + if (!device) { + CanInstPtr = &CanPs0; + } else { + CanInstPtr = &CanPs1; + } + mode = XCanPs_GetMode(CanInstPtr); + if (mode != XCANPS_MODE_LOOPBACK) { +#ifdef CAN_DEBUG + print("\nNot in loopback mode, can't run self test"); +#endif + return FAILURE; + } + + // Populate CAN packet + can_packet_t packet; + packet.message_id = 1; + packet.num_bytes = FRAME_DATA_LENGTH; + int i; + for (i = 0; i < FRAME_DATA_LENGTH; i++) { + data[i] = i; + } + memcpy(packet.buffer, data, FRAME_DATA_LENGTH); + + // Send fake packet of data + Status = can_send(packet, FRAME_DATA_LENGTH, device); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Check fake packet of data is received correctly + Status = can_checkpacket(device); + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} diff --git a/sdk/app_cpu1/common/drv/can.h b/sdk/app_cpu1/common/drv/can.h new file mode 100644 index 00000000..39c63690 --- /dev/null +++ b/sdk/app_cpu1/common/drv/can.h @@ -0,0 +1,85 @@ +#ifndef CAN_H +#define CAN_H + +#include "xcanps.h" +#include + +/* + * The Baud Rate Prescaler Register (BRPR) and Bit Timing Register (BTR) + * are setup such that CAN baud rate equals 500 Kbps, assuming that the + * the CAN clock is 200 MHz. The user needs to modify these values based on + * the desired baud rate and the CAN clock frequency. For more information + * see the CAN 2.0A, CAN 2.0B, ISO 11898-1 specifications. + */ + +/* + * Timing parameters to be set in the Bit Timing Register (BTR). + * These values are for a 500 Kbps baudrate assuming the CAN input clock frequency + * is 24 MHz. + * + * The value of BTR register after using these defaults is 0x1C. According to the Zynq-7000 + * Reference Manual, the actual value is one more than the value written to the register. + * Thus, we write a value of 12 and 1 for the first and second time segment, respectively, + * to have an actual value of 13 and 2. + */ +#define DEFAULT_BTR_SYNCJUMPWIDTH 3 +#define DEFAULT_BTR_SECOND_TIMESEGMENT 1 +#define DEFAULT_BTR_FIRST_TIMESEGMENT 12 + +/* + * The Baud rate Prescalar value in the Baud Rate Prescaler Register (BRPR) + * needs to be set based on the input clock frequency to the CAN core and + * the desired CAN baud rate. + * This value is for a 500 Kbps baudrate assuming the CAN input clock frequency + * is 24 MHz. + * + * The value of the BRPR after using this default is 0x02. According to the Zync-7000 + * Reference Manual, the actual value is one more than the value written to the register. + * Thus, we write a value of 2 to the register, but the actual value is 3, which it should be. + */ +#define DEFAULT_BAUD_PRESCALAR 16 +#define DEFAULT_CAN_MESSAGE_ID 1 + +typedef enum { + CAN0, + CAN1, +} can_peripheral_t; + +// Different CAN modes +typedef enum { + CAN_CONFIG = XCANPS_MODE_CONFIG, + CAN_LOOPBACK = XCANPS_MODE_LOOPBACK, + CAN_NORMAL = XCANPS_MODE_NORMAL, + CAN_SLEEP = XCANPS_MODE_SLEEP, + CAN_SNOOP = XCANPS_MODE_SNOOP, +} can_mode_t; + +// Struct representing an entire CAN Packet +typedef struct can_packets_t { + int message_id; + int num_bytes; + uint8_t buffer[8]; +} can_packet_t; + +// Setter methods, useful for configuring the CAN peripheral +int can_setmode(can_mode_t MODE, can_peripheral_t device); +int can_setbaud(int rate, can_peripheral_t device); +int can_set_btr(uint8_t sjw, uint8_t ts1, uint8_t ts2, can_peripheral_t device); +//int can_set_peripheral(int device_id); + +// Initialize the CAN peripheral +int can_init(int device_id); +int can_deinit(); + +// Send and get CAN packets +int can_send(can_packet_t packet, uint32_t num_bytes, can_peripheral_t device); +int can_rcv(uint8_t buffer[8], can_peripheral_t device); + +// Useful debugging functionality +void can_print_mode(can_peripheral_t device); +void can_print_peripheral(); + +// Sanity check that hardware working +int can_loopback_test(can_peripheral_t device); + +#endif // CAN_H