From 287d02aa95d14ac944dd9a11be709e3e9f017de8 Mon Sep 17 00:00:00 2001 From: Mohamed-Dek A Mohamed Date: Tue, 18 Feb 2025 13:54:17 -0600 Subject: [PATCH 1/6] updates verilog Zynq setup to generate CAN bsp drivers --- hw/amdc_revf.bd | 1238 +++++++++++++++++---------------- sdk/app_cpu1/common/drv/can.c | 368 ++++++++++ sdk/app_cpu1/common/drv/can.h | 79 +++ 3 files changed, 1081 insertions(+), 604 deletions(-) create mode 100644 sdk/app_cpu1/common/drv/can.c create mode 100644 sdk/app_cpu1/common/drv/can.h diff --git a/hw/amdc_revf.bd b/hw/amdc_revf.bd index 35a06aeb..5c21e46f 100644 --- a/hw/amdc_revf.bd +++ b/hw/amdc_revf.bd @@ -829,7 +829,7 @@ "value": "666.666687" }, "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { - "value": "10.000000" + "value": "100.000000" }, "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { "value": "10.158730" @@ -900,11 +900,29 @@ "PCW_APU_PERIPHERAL_FREQMHZ": { "value": "667" }, + "PCW_CAN0_CAN0_IO": { + "value": "MIO 30 .. 31" + }, + "PCW_CAN0_GRP_CLK_ENABLE": { + "value": "0" + }, "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN1_CAN1_IO": { + "value": "MIO 32 .. 33" + }, + "PCW_CAN1_GRP_CLK_ENABLE": { "value": "0" }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_CAN_PERIPHERAL_FREQMHZ": { + "value": "100" + }, "PCW_CAN_PERIPHERAL_VALID": { - "value": "0" + "value": "1" }, "PCW_CLK0_FREQ": { "value": "200000000" @@ -970,7 +988,10 @@ "value": "Share reset pin" }, "PCW_EN_CAN0": { - "value": "0" + "value": "1" + }, + "PCW_EN_CAN1": { + "value": "1" }, "PCW_EN_CLK0_PORT": { "value": "1" @@ -990,6 +1011,9 @@ "PCW_EN_EMIO_CAN0": { "value": "0" }, + "PCW_EN_EMIO_CAN1": { + "value": "0" + }, "PCW_EN_EMIO_CD_SDIO1": { "value": "1" }, @@ -1558,10 +1582,16 @@ "value": "54" }, "PCW_MIO_TREE_PERIPHERALS": { - "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0" + "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#CAN 0#CAN 0#CAN 1#CAN 1#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0" }, "PCW_MIO_TREE_SIGNALS": { - "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#rx#tx#mdc#mdio" + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#rx#tx#tx#rx#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#rx#tx#mdc#mdio" + }, + "PCW_P2F_CAN0_INTR": { + "value": "1" + }, + "PCW_P2F_CAN1_INTR": { + "value": "1" }, "PCW_P2F_UART0_INTR": { "value": "1" @@ -3061,17 +3091,17 @@ "s00_data_fifo/M_AXI" ] }, - "auto_pc_to_s00_data_fifo": { - "interface_ports": [ - "s00_data_fifo/S_AXI", - "auto_pc/M_AXI" - ] - }, "s00_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_s00_data_fifo": { + "interface_ports": [ + "s00_data_fifo/S_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -3709,17 +3739,17 @@ } }, "interface_nets": { - "m07_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m07_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m07_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3797,17 +3827,17 @@ } }, "interface_nets": { - "auto_pc_to_m08_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m08_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m08_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -3885,17 +3915,17 @@ } }, "interface_nets": { - "m09_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m09_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m09_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4027,17 +4057,17 @@ } }, "interface_nets": { - "m11_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m11_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m11_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4203,17 +4233,17 @@ } }, "interface_nets": { - "auto_pc_to_m13_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m13_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m13_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4291,17 +4321,17 @@ } }, "interface_nets": { - "auto_pc_to_m14_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m14_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m14_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4433,17 +4463,17 @@ } }, "interface_nets": { - "m16_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m16_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m16_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4521,17 +4551,17 @@ } }, "interface_nets": { - "m17_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m17_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m17_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4609,17 +4639,17 @@ } }, "interface_nets": { - "auto_pc_to_m18_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m18_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m18_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4839,17 +4869,17 @@ } }, "interface_nets": { - "m21_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m21_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m21_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5015,17 +5045,17 @@ } }, "interface_nets": { - "auto_pc_to_m23_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m23_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m23_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5103,17 +5133,17 @@ } }, "interface_nets": { - "auto_pc_to_m24_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m24_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m24_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5245,17 +5275,17 @@ } }, "interface_nets": { - "auto_pc_to_m26_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m26_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m26_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5333,17 +5363,17 @@ } }, "interface_nets": { - "auto_pc_to_m27_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m27_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m27_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5421,17 +5451,17 @@ } }, "interface_nets": { - "m28_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m28_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m28_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5509,17 +5539,17 @@ } }, "interface_nets": { - "auto_pc_to_m29_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m29_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m29_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5685,17 +5715,17 @@ } }, "interface_nets": { - "auto_pc_to_m31_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m31_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m31_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -6039,532 +6069,532 @@ } }, "interface_nets": { - "m00_couplers_to_ps7_0_axi_periph": { + "xbar_to_i00_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "ps7_0_axi_periph_to_s00_couplers": { + "xbar_to_i01_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m00_couplers": { + "xbar_to_i02_couplers": { "interface_ports": [ - "tier2_xbar_0/M00_AXI", - "m00_couplers/S_AXI" + "xbar/M02_AXI", + "i02_couplers/S_AXI" ] }, - "m01_couplers_to_ps7_0_axi_periph": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "m02_couplers_to_ps7_0_axi_periph": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, - "tier2_xbar_0_to_m01_couplers": { + "xbar_to_i03_couplers": { "interface_ports": [ - "tier2_xbar_0/M01_AXI", - "m01_couplers/S_AXI" + "xbar/M03_AXI", + "i03_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m02_couplers": { + "i03_couplers_to_tier2_xbar_3": { "interface_ports": [ - "tier2_xbar_0/M02_AXI", - "m02_couplers/S_AXI" + "i03_couplers/M_AXI", + "tier2_xbar_3/S00_AXI" ] }, - "m03_couplers_to_ps7_0_axi_periph": { + "xbar_to_i04_couplers": { "interface_ports": [ - "M03_AXI", - "m03_couplers/M_AXI" + "xbar/M04_AXI", + "i04_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m03_couplers": { + "i04_couplers_to_tier2_xbar_4": { "interface_ports": [ - "tier2_xbar_0/M03_AXI", - "m03_couplers/S_AXI" + "i04_couplers/M_AXI", + "tier2_xbar_4/S00_AXI" ] }, - "m04_couplers_to_ps7_0_axi_periph": { + "m31_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M04_AXI", - "m04_couplers/M_AXI" + "M31_AXI", + "m31_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m04_couplers": { + "tier2_xbar_1_to_m13_couplers": { "interface_ports": [ - "tier2_xbar_0/M04_AXI", - "m04_couplers/S_AXI" + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" ] }, - "m05_couplers_to_ps7_0_axi_periph": { + "m14_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M05_AXI", - "m05_couplers/M_AXI" + "M14_AXI", + "m14_couplers/M_AXI" ] }, - "m06_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m14_couplers": { "interface_ports": [ - "M06_AXI", - "m06_couplers/M_AXI" + "tier2_xbar_1/M06_AXI", + "m14_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m05_couplers": { + "m15_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M05_AXI", - "m05_couplers/S_AXI" + "M15_AXI", + "m15_couplers/M_AXI" ] }, - "m07_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m15_couplers": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "tier2_xbar_1/M07_AXI", + "m15_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m06_couplers": { + "m16_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M06_AXI", - "m06_couplers/S_AXI" + "M16_AXI", + "m16_couplers/M_AXI" ] }, - "tier2_xbar_0_to_m07_couplers": { + "tier2_xbar_2_to_m16_couplers": { "interface_ports": [ - "tier2_xbar_0/M07_AXI", - "m07_couplers/S_AXI" + "tier2_xbar_2/M00_AXI", + "m16_couplers/S_AXI" ] }, - "m08_couplers_to_ps7_0_axi_periph": { + "m17_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "M17_AXI", + "m17_couplers/M_AXI" ] }, - "m09_couplers_to_ps7_0_axi_periph": { + "m18_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "M18_AXI", + "m18_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m08_couplers": { + "tier2_xbar_2_to_m17_couplers": { "interface_ports": [ - "tier2_xbar_1/M00_AXI", - "m08_couplers/S_AXI" + "tier2_xbar_2/M01_AXI", + "m17_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m09_couplers": { + "tier2_xbar_2_to_m18_couplers": { "interface_ports": [ - "tier2_xbar_1/M01_AXI", - "m09_couplers/S_AXI" + "tier2_xbar_2/M02_AXI", + "m18_couplers/S_AXI" ] }, - "m10_couplers_to_ps7_0_axi_periph": { + "m19_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "M19_AXI", + "m19_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m10_couplers": { + "m20_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M02_AXI", - "m10_couplers/S_AXI" + "M20_AXI", + "m20_couplers/M_AXI" ] }, - "m11_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m19_couplers": { "interface_ports": [ - "M11_AXI", - "m11_couplers/M_AXI" + "tier2_xbar_2/M03_AXI", + "m19_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m11_couplers": { + "m21_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M03_AXI", - "m11_couplers/S_AXI" + "M21_AXI", + "m21_couplers/M_AXI" ] }, - "m12_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m20_couplers": { "interface_ports": [ - "M12_AXI", - "m12_couplers/M_AXI" + "tier2_xbar_2/M04_AXI", + "m20_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m24_couplers": { + "tier2_xbar_2_to_m21_couplers": { "interface_ports": [ - "tier2_xbar_3/M00_AXI", - "m24_couplers/S_AXI" + "tier2_xbar_2/M05_AXI", + "m21_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m12_couplers": { + "m22_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M04_AXI", - "m12_couplers/S_AXI" + "M22_AXI", + "m22_couplers/M_AXI" ] }, - "m13_couplers_to_ps7_0_axi_periph": { + "m23_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M13_AXI", - "m13_couplers/M_AXI" + "M23_AXI", + "m23_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m13_couplers": { + "tier2_xbar_2_to_m22_couplers": { "interface_ports": [ - "tier2_xbar_1/M05_AXI", - "m13_couplers/S_AXI" + "tier2_xbar_2/M06_AXI", + "m22_couplers/S_AXI" ] }, - "m14_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m23_couplers": { "interface_ports": [ - "M14_AXI", - "m14_couplers/M_AXI" + "tier2_xbar_2/M07_AXI", + "m23_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m14_couplers": { + "m24_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M06_AXI", - "m14_couplers/S_AXI" + "M24_AXI", + "m24_couplers/M_AXI" ] }, - "m15_couplers_to_ps7_0_axi_periph": { + "m25_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M15_AXI", - "m15_couplers/M_AXI" + "M25_AXI", + "m25_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m15_couplers": { + "tier2_xbar_3_to_m24_couplers": { "interface_ports": [ - "tier2_xbar_1/M07_AXI", - "m15_couplers/S_AXI" + "tier2_xbar_3/M00_AXI", + "m24_couplers/S_AXI" ] }, - "m16_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m25_couplers": { "interface_ports": [ - "M16_AXI", - "m16_couplers/M_AXI" + "tier2_xbar_3/M01_AXI", + "m25_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m16_couplers": { + "m26_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M00_AXI", - "m16_couplers/S_AXI" + "M26_AXI", + "m26_couplers/M_AXI" ] }, - "m17_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m26_couplers": { "interface_ports": [ - "M17_AXI", - "m17_couplers/M_AXI" + "tier2_xbar_3/M02_AXI", + "m26_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m17_couplers": { + "m27_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M01_AXI", - "m17_couplers/S_AXI" + "M27_AXI", + "m27_couplers/M_AXI" ] }, - "m18_couplers_to_ps7_0_axi_periph": { + "m28_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M18_AXI", - "m18_couplers/M_AXI" + "M28_AXI", + "m28_couplers/M_AXI" ] }, - "m19_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m27_couplers": { "interface_ports": [ - "M19_AXI", - "m19_couplers/M_AXI" + "tier2_xbar_3/M03_AXI", + "m27_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m18_couplers": { + "m29_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M02_AXI", - "m18_couplers/S_AXI" + "M29_AXI", + "m29_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m19_couplers": { + "tier2_xbar_3_to_m28_couplers": { "interface_ports": [ - "tier2_xbar_2/M03_AXI", - "m19_couplers/S_AXI" + "tier2_xbar_3/M04_AXI", + "m28_couplers/S_AXI" ] }, - "m20_couplers_to_ps7_0_axi_periph": { + "m30_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M20_AXI", - "m20_couplers/M_AXI" + "M30_AXI", + "m30_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m20_couplers": { + "tier2_xbar_3_to_m29_couplers": { "interface_ports": [ - "tier2_xbar_2/M04_AXI", - "m20_couplers/S_AXI" + "tier2_xbar_3/M05_AXI", + "m29_couplers/S_AXI" ] }, - "m21_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m30_couplers": { "interface_ports": [ - "M21_AXI", - "m21_couplers/M_AXI" + "tier2_xbar_3/M06_AXI", + "m30_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m21_couplers": { + "m32_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M05_AXI", - "m21_couplers/S_AXI" + "M32_AXI", + "m32_couplers/M_AXI" ] }, - "m22_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_3_to_m31_couplers": { "interface_ports": [ - "M22_AXI", - "m22_couplers/M_AXI" + "tier2_xbar_3/M07_AXI", + "m31_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m22_couplers": { + "tier2_xbar_4_to_m32_couplers": { "interface_ports": [ - "tier2_xbar_2/M06_AXI", - "m22_couplers/S_AXI" + "tier2_xbar_4/M00_AXI", + "m32_couplers/S_AXI" ] }, - "m23_couplers_to_ps7_0_axi_periph": { + "m33_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M23_AXI", - "m23_couplers/M_AXI" + "M33_AXI", + "m33_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m23_couplers": { + "m34_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M07_AXI", - "m23_couplers/S_AXI" + "M34_AXI", + "m34_couplers/M_AXI" ] }, - "m24_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m33_couplers": { "interface_ports": [ - "M24_AXI", - "m24_couplers/M_AXI" + "tier2_xbar_4/M01_AXI", + "m33_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m37_couplers": { + "tier2_xbar_4_to_m34_couplers": { "interface_ports": [ - "tier2_xbar_4/M05_AXI", - "m37_couplers/S_AXI" + "tier2_xbar_4/M02_AXI", + "m34_couplers/S_AXI" ] }, - "xbar_to_i00_couplers": { + "m35_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M00_AXI", - "i00_couplers/S_AXI" + "M35_AXI", + "m35_couplers/M_AXI" ] }, - "i00_couplers_to_tier2_xbar_0": { + "tier2_xbar_4_to_m35_couplers": { "interface_ports": [ - "i00_couplers/M_AXI", - "tier2_xbar_0/S00_AXI" + "tier2_xbar_4/M03_AXI", + "m35_couplers/S_AXI" ] }, - "xbar_to_i01_couplers": { + "m36_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M01_AXI", - "i01_couplers/S_AXI" + "M36_AXI", + "m36_couplers/M_AXI" ] }, - "xbar_to_i02_couplers": { + "tier2_xbar_4_to_m36_couplers": { "interface_ports": [ - "xbar/M02_AXI", - "i02_couplers/S_AXI" + "tier2_xbar_4/M04_AXI", + "m36_couplers/S_AXI" ] }, - "i01_couplers_to_tier2_xbar_1": { + "m37_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i01_couplers/M_AXI", - "tier2_xbar_1/S00_AXI" + "M37_AXI", + "m37_couplers/M_AXI" ] }, - "i02_couplers_to_tier2_xbar_2": { + "tier2_xbar_4_to_m37_couplers": { "interface_ports": [ - "i02_couplers/M_AXI", - "tier2_xbar_2/S00_AXI" + "tier2_xbar_4/M05_AXI", + "m37_couplers/S_AXI" ] }, - "xbar_to_i03_couplers": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ - "xbar/M03_AXI", - "i03_couplers/S_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, - "i03_couplers_to_tier2_xbar_3": { + "m00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i03_couplers/M_AXI", - "tier2_xbar_3/S00_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, - "xbar_to_i04_couplers": { + "s00_couplers_to_xbar": { "interface_ports": [ - "xbar/M04_AXI", - "i04_couplers/S_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] }, - "i04_couplers_to_tier2_xbar_4": { + "tier2_xbar_0_to_m00_couplers": { "interface_ports": [ - "i04_couplers/M_AXI", - "tier2_xbar_4/S00_AXI" + "tier2_xbar_0/M00_AXI", + "m00_couplers/S_AXI" ] }, - "m25_couplers_to_ps7_0_axi_periph": { + "m01_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M25_AXI", - "m25_couplers/M_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m25_couplers": { + "tier2_xbar_0_to_m01_couplers": { "interface_ports": [ - "tier2_xbar_3/M01_AXI", - "m25_couplers/S_AXI" + "tier2_xbar_0/M01_AXI", + "m01_couplers/S_AXI" ] }, - "m26_couplers_to_ps7_0_axi_periph": { + "m02_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M26_AXI", - "m26_couplers/M_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m26_couplers": { + "m03_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M02_AXI", - "m26_couplers/S_AXI" + "M03_AXI", + "m03_couplers/M_AXI" ] }, - "m27_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m02_couplers": { "interface_ports": [ - "M27_AXI", - "m27_couplers/M_AXI" + "tier2_xbar_0/M02_AXI", + "m02_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m27_couplers": { + "tier2_xbar_0_to_m03_couplers": { "interface_ports": [ - "tier2_xbar_3/M03_AXI", - "m27_couplers/S_AXI" + "tier2_xbar_0/M03_AXI", + "m03_couplers/S_AXI" ] }, - "m28_couplers_to_ps7_0_axi_periph": { + "m04_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M28_AXI", - "m28_couplers/M_AXI" + "M04_AXI", + "m04_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m28_couplers": { + "tier2_xbar_0_to_m04_couplers": { "interface_ports": [ - "tier2_xbar_3/M04_AXI", - "m28_couplers/S_AXI" + "tier2_xbar_0/M04_AXI", + "m04_couplers/S_AXI" ] }, - "m29_couplers_to_ps7_0_axi_periph": { + "m05_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M29_AXI", - "m29_couplers/M_AXI" + "M05_AXI", + "m05_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m29_couplers": { + "tier2_xbar_0_to_m05_couplers": { "interface_ports": [ - "tier2_xbar_3/M05_AXI", - "m29_couplers/S_AXI" + "tier2_xbar_0/M05_AXI", + "m05_couplers/S_AXI" ] }, - "m30_couplers_to_ps7_0_axi_periph": { + "m06_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M30_AXI", - "m30_couplers/M_AXI" + "M06_AXI", + "m06_couplers/M_AXI" ] }, - "m31_couplers_to_ps7_0_axi_periph": { + "m07_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M31_AXI", - "m31_couplers/M_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, - "tier2_xbar_3_to_m30_couplers": { + "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ - "tier2_xbar_3/M06_AXI", - "m30_couplers/S_AXI" + "tier2_xbar_0/M06_AXI", + "m06_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m31_couplers": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "tier2_xbar_3/M07_AXI", - "m31_couplers/S_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" ] }, - "m32_couplers_to_ps7_0_axi_periph": { + "m08_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M32_AXI", - "m32_couplers/M_AXI" + "M08_AXI", + "m08_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m32_couplers": { + "m09_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M00_AXI", - "m32_couplers/S_AXI" + "M09_AXI", + "m09_couplers/M_AXI" ] }, - "m33_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m08_couplers": { "interface_ports": [ - "M33_AXI", - "m33_couplers/M_AXI" + "tier2_xbar_1/M00_AXI", + "m08_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m33_couplers": { + "tier2_xbar_1_to_m09_couplers": { "interface_ports": [ - "tier2_xbar_4/M01_AXI", - "m33_couplers/S_AXI" + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" ] }, - "m34_couplers_to_ps7_0_axi_periph": { + "m10_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M34_AXI", - "m34_couplers/M_AXI" + "M10_AXI", + "m10_couplers/M_AXI" ] }, - "m35_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m10_couplers": { "interface_ports": [ - "M35_AXI", - "m35_couplers/M_AXI" + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m34_couplers": { + "m11_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M02_AXI", - "m34_couplers/S_AXI" + "M11_AXI", + "m11_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m35_couplers": { + "m12_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M03_AXI", - "m35_couplers/S_AXI" + "M12_AXI", + "m12_couplers/M_AXI" ] }, - "m36_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m11_couplers": { "interface_ports": [ - "M36_AXI", - "m36_couplers/M_AXI" + "tier2_xbar_1/M03_AXI", + "m11_couplers/S_AXI" ] }, - "m37_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m12_couplers": { "interface_ports": [ - "M37_AXI", - "m37_couplers/M_AXI" + "tier2_xbar_1/M04_AXI", + "m12_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m36_couplers": { + "m13_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M04_AXI", - "m36_couplers/S_AXI" + "M13_AXI", + "m13_couplers/M_AXI" ] } }, @@ -7161,6 +7191,18 @@ } }, "interface_nets": { + "Conn1": { + "interface_ports": [ + "M00_AXI", + "ps7_0_axi_periph/M00_AXI" + ] + }, + "Conn17": { + "interface_ports": [ + "M17_AXI", + "ps7_0_axi_periph/M17_AXI" + ] + }, "Conn22": { "interface_ports": [ "M22_AXI", @@ -7191,30 +7233,30 @@ "ps7_0_axi_periph/M05_AXI" ] }, - "Conn29": { - "interface_ports": [ - "M33_AXI", - "ps7_0_axi_periph/M33_AXI" - ] - }, "Conn19": { "interface_ports": [ "M19_AXI", "ps7_0_axi_periph/M19_AXI" ] }, - "Conn9": { - "interface_ports": [ - "M08_AXI", - "ps7_0_axi_periph/M08_AXI" - ] - }, "Conn13": { "interface_ports": [ "M12_AXI", "ps7_0_axi_periph/M12_AXI" ] }, + "Conn29": { + "interface_ports": [ + "M33_AXI", + "ps7_0_axi_periph/M33_AXI" + ] + }, + "Conn9": { + "interface_ports": [ + "M08_AXI", + "ps7_0_axi_periph/M08_AXI" + ] + }, "Conn16": { "interface_ports": [ "M16_AXI", @@ -7245,28 +7287,22 @@ "ps7_0_axi_periph/M36_AXI" ] }, - "ps7_0_axi_periph_M37_AXI": { - "interface_ports": [ - "M37_AXI", - "ps7_0_axi_periph/M37_AXI" - ] - }, - "Conn17": { + "processing_system7_0_DDR": { "interface_ports": [ - "M17_AXI", - "ps7_0_axi_periph/M17_AXI" + "DDR", + "processing_system7_0/DDR" ] }, - "Conn1": { + "ps7_0_axi_periph_M37_AXI": { "interface_ports": [ - "M00_AXI", - "ps7_0_axi_periph/M00_AXI" + "M37_AXI", + "ps7_0_axi_periph/M37_AXI" ] }, - "processing_system7_0_DDR": { + "Conn10": { "interface_ports": [ - "DDR", - "processing_system7_0/DDR" + "M09_AXI", + "ps7_0_axi_periph/M09_AXI" ] }, "Conn18": { @@ -7281,34 +7317,22 @@ "ps7_0_axi_periph/M32_AXI" ] }, - "Conn10": { - "interface_ports": [ - "M09_AXI", - "ps7_0_axi_periph/M09_AXI" - ] - }, "ps7_0_axi_periph_M30_AXI": { "interface_ports": [ "M30_AXI", "ps7_0_axi_periph/M30_AXI" ] }, - "Conn21": { - "interface_ports": [ - "M21_AXI", - "ps7_0_axi_periph/M21_AXI" - ] - }, "Conn2": { "interface_ports": [ "M01_AXI", "ps7_0_axi_periph/M01_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "Conn21": { "interface_ports": [ - "FIXED_IO", - "processing_system7_0/FIXED_IO" + "M21_AXI", + "ps7_0_axi_periph/M21_AXI" ] }, "Conn3": { @@ -7317,16 +7341,16 @@ "ps7_0_axi_periph/M02_AXI" ] }, - "Conn8": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "M07_AXI", - "ps7_0_axi_periph/M07_AXI" + "FIXED_IO", + "processing_system7_0/FIXED_IO" ] }, - "Conn14": { + "Conn8": { "interface_ports": [ - "M14_AXI", - "ps7_0_axi_periph/M14_AXI" + "M07_AXI", + "ps7_0_axi_periph/M07_AXI" ] }, "Conn11": { @@ -7341,10 +7365,10 @@ "ps7_0_axi_periph/M25_AXI" ] }, - "ps7_0_axi_periph_M13_AXI": { + "Conn14": { "interface_ports": [ - "M13_AXI", - "ps7_0_axi_periph/M13_AXI" + "M14_AXI", + "ps7_0_axi_periph/M14_AXI" ] }, "Conn20": { @@ -7353,16 +7377,28 @@ "ps7_0_axi_periph/M20_AXI" ] }, + "Conn7": { + "interface_ports": [ + "M06_AXI", + "ps7_0_axi_periph/M06_AXI" + ] + }, + "ps7_0_axi_periph_M13_AXI": { + "interface_ports": [ + "M13_AXI", + "ps7_0_axi_periph/M13_AXI" + ] + }, "Conn24": { "interface_ports": [ "M24_AXI", "ps7_0_axi_periph/M24_AXI" ] }, - "Conn7": { + "Conn5": { "interface_ports": [ - "M06_AXI", - "ps7_0_axi_periph/M06_AXI" + "M04_AXI", + "ps7_0_axi_periph/M04_AXI" ] }, "Conn26": { @@ -7371,10 +7407,10 @@ "ps7_0_axi_periph/M26_AXI" ] }, - "Conn5": { + "ps7_0_axi_periph_M31_AXI": { "interface_ports": [ - "M04_AXI", - "ps7_0_axi_periph/M04_AXI" + "M31_AXI", + "ps7_0_axi_periph/M31_AXI" ] }, "Conn4": { @@ -7389,12 +7425,6 @@ "ps7_0_axi_periph/M29_AXI" ] }, - "ps7_0_axi_periph_M31_AXI": { - "interface_ports": [ - "M31_AXI", - "ps7_0_axi_periph/M31_AXI" - ] - }, "ps7_0_axi_periph_M35_AXI": { "interface_ports": [ "M35_AXI", @@ -7648,18 +7678,18 @@ } }, "interface_nets": { - "Conn1": { - "interface_ports": [ - "S00_AXI2", - "amdc_inv_status_mux_0/S00_AXI" - ] - }, "ps7_0_axi_periph_M02_AXI": { "interface_ports": [ "S00_AXI", "amdc_inverters_0/S00_AXI" ] }, + "Conn1": { + "interface_ports": [ + "S00_AXI2", + "amdc_inv_status_mux_0/S00_AXI" + ] + }, "ps7_0_axi_periph_M06_AXI": { "interface_ports": [ "S00_AXI1", @@ -8003,17 +8033,17 @@ } }, "interface_nets": { - "hier_ps_M13_AXI": { - "interface_ports": [ - "S00_AXI1", - "amdc_ild1420_1/S00_AXI" - ] - }, "hier_ps_M12_AXI": { "interface_ports": [ "S00_AXI", "amdc_ild1420_0/S00_AXI" ] + }, + "hier_ps_M13_AXI": { + "interface_ports": [ + "S00_AXI1", + "amdc_ild1420_1/S00_AXI" + ] } }, "nets": { @@ -8187,16 +8217,16 @@ } }, "interface_nets": { - "S00_AXI6_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -8205,6 +8235,12 @@ "hier_ild1420_0/S00_AXI1" ] }, + "hier_ps_M48_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" + ] + }, "S00_AXI1_1": { "interface_ports": [ "S00_AXI1", @@ -8216,12 +8252,6 @@ "S00_AXI3", "hier_ild1420_0/S00_AXI" ] - }, - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] } }, "nets": { @@ -8710,34 +8740,34 @@ } }, "interface_nets": { + "S00_AXI6_1": { + "interface_ports": [ + "S00_AXI6", + "amdc_amds_0/S00_AXI" + ] + }, "S00_AXI5_1": { "interface_ports": [ "S00_AXI5", "amdc_gpio_direct_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] }, - "S00_AXI6_1": { + "hier_ps_M48_AXI": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] }, "S00_AXI1_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" - ] - }, - "S00_AXI3_1": { - "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -9049,17 +9079,17 @@ } }, "interface_nets": { - "hier_ps_M13_AXI": { - "interface_ports": [ - "S00_AXI1", - "amdc_ild1420_1/S00_AXI" - ] - }, "hier_ps_M12_AXI": { "interface_ports": [ "S00_AXI", "amdc_ild1420_0/S00_AXI" ] + }, + "hier_ps_M13_AXI": { + "interface_ports": [ + "S00_AXI1", + "amdc_ild1420_1/S00_AXI" + ] } }, "nets": { @@ -9245,18 +9275,18 @@ "amdc_gpio_direct_0/S00_AXI" ] }, - "S00_AXI3_1": { - "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" - ] - }, "S00_AXI6_1": { "interface_ports": [ "S00_AXI6", "amdc_amds_0/S00_AXI" ] }, + "S00_AXI3_1": { + "interface_ports": [ + "S00_AXI3", + "hier_ild1420_0/S00_AXI" + ] + }, "S00_AXI4_1": { "interface_ports": [ "S00_AXI4", @@ -9756,28 +9786,22 @@ } }, "interface_nets": { - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, "S00_AXI6_1": { "interface_ports": [ "S00_AXI6", "amdc_amds_0/S00_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] }, "S00_AXI4_1": { @@ -9786,6 +9810,12 @@ "hier_ild1420_0/S00_AXI1" ] }, + "hier_ps_M48_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" + ] + }, "S00_AXI1_1": { "interface_ports": [ "S00_AXI1", @@ -9994,208 +10024,208 @@ } }, "interface_nets": { - "hier_ps_M31_AXI": { + "S00_AXI4_1": { "interface_ports": [ - "hier_ps/M31_AXI", - "hier_gpio_2/S00_AXI5" + "hier_gpio_0/S00_AXI4", + "hier_ps/M13_AXI" ] }, - "S00_AXI1_5": { + "S00_AXI2_1": { "interface_ports": [ - "hier_gpio_3/S00_AXI1", - "hier_ps/M26_AXI" + "hier_powerstack/S00_AXI2", + "hier_ps/M08_AXI" ] }, - "hier_ps_M37_AXI1": { + "S00_AXI1_2": { "interface_ports": [ - "hier_ps/M37_AXI", - "hier_gpio_3/S00_AXI6" + "hier_gpio_0/S00_AXI1", + "hier_ps/M11_AXI" ] }, - "S00_AXI3_3": { + "S00_AXI_5": { "interface_ports": [ - "hier_gpio_2/S00_AXI3", - "hier_ps/M22_AXI" + "hier_gpio_3/S00_AXI", + "hier_ps/M24_AXI" ] }, - "hier_ps_M37_AXI": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "amdc_dac_0/S00_AXI", - "hier_ps/M05_AXI" + "FIXED_IO", + "hier_ps/FIXED_IO" ] }, - "S00_AXI3_2": { + "hier_ps_M35_AXI": { "interface_ports": [ - "hier_gpio_1/S00_AXI3", - "hier_ps/M17_AXI" + "amdc_leds_0/S00_AXI", + "hier_ps/M03_AXI" ] }, - "hier_ps_M34_AXI": { + "hier_ps_M29_AXI": { "interface_ports": [ - "amdc_encoder_0/S00_AXI", - "hier_ps/M02_AXI" + "hier_ps/M29_AXI", + "hier_gpio_0/S00_AXI5" ] }, - "processing_system7_0_DDR": { + "hier_ps_M34_AXI1": { "interface_ports": [ - "DDR", - "hier_ps/DDR" + "hier_ps/M34_AXI", + "hier_gpio_2/S00_AXI6" ] }, - "hier_ps_M36_AXI1": { + "S00_AXI_2": { "interface_ports": [ - "hier_ps/M36_AXI", - "hier_gpio_1/S00_AXI6" + "hier_gpio_0/S00_AXI", + "hier_ps/M09_AXI" ] }, - "hier_ps_M30_AXI": { + "S00_AXI_3": { "interface_ports": [ - "hier_ps/M30_AXI", - "hier_gpio_1/S00_AXI5" + "hier_gpio_1/S00_AXI", + "hier_ps/M14_AXI" ] }, - "S00_AXI1_3": { + "hier_ps_M36_AXI": { "interface_ports": [ - "hier_gpio_1/S00_AXI1", - "hier_ps/M16_AXI" + "amdc_adc_0/S00_AXI", + "hier_ps/M04_AXI" ] }, - "S00_AXI1_1": { + "hier_ps_M37_AXI": { "interface_ports": [ - "hier_powerstack/S00_AXI1", - "hier_ps/M07_AXI" + "amdc_dac_0/S00_AXI", + "hier_ps/M05_AXI" ] }, - "S00_AXI4_4": { + "S00_AXI1_5": { "interface_ports": [ - "hier_gpio_3/S00_AXI4", - "hier_ps/M28_AXI" + "hier_gpio_3/S00_AXI1", + "hier_ps/M26_AXI" ] }, - "S00_AXI1_4": { + "hier_ps_M37_AXI1": { "interface_ports": [ - "hier_gpio_2/S00_AXI1", - "hier_ps/M21_AXI" + "hier_ps/M37_AXI", + "hier_gpio_3/S00_AXI6" ] }, - "hier_ps_M35_AXI1": { + "S00_AXI_4": { "interface_ports": [ - "hier_ps/M35_AXI", - "hier_gpio_0/S00_AXI6" + "hier_gpio_2/S00_AXI", + "hier_ps/M19_AXI" ] }, - "S00_AXI4_2": { + "hier_ps_M32_AXI1": { "interface_ports": [ - "hier_gpio_1/S00_AXI4", - "hier_ps/M18_AXI" + "hier_ps/M32_AXI", + "hier_gpio_3/S00_AXI5" ] }, - "S00_AXI3_4": { + "S00_AXI4_3": { "interface_ports": [ - "hier_gpio_3/S00_AXI3", - "hier_ps/M27_AXI" + "hier_gpio_2/S00_AXI4", + "hier_ps/M23_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI_1": { "interface_ports": [ - "hier_gpio_0/S00_AXI3", - "hier_ps/M12_AXI" + "hier_powerstack/S00_AXI", + "hier_ps/M06_AXI" ] }, - "hier_ps_M35_AXI": { + "hier_ps_M34_AXI": { "interface_ports": [ - "amdc_leds_0/S00_AXI", - "hier_ps/M03_AXI" + "amdc_encoder_0/S00_AXI", + "hier_ps/M02_AXI" ] }, - "hier_ps_M33_AXI1": { + "hier_ps_M31_AXI": { "interface_ports": [ - "amdc_timing_manager_0/S00_AXI", - "hier_ps/M33_AXI" + "hier_ps/M31_AXI", + "hier_gpio_2/S00_AXI5" ] }, - "S00_AXI_1": { + "hier_ps_M33_AXI1": { "interface_ports": [ - "hier_powerstack/S00_AXI", - "hier_ps/M06_AXI" + "amdc_timing_manager_0/S00_AXI", + "hier_ps/M33_AXI" ] }, - "S00_AXI_5": { + "processing_system7_0_DDR": { "interface_ports": [ - "hier_gpio_3/S00_AXI", - "hier_ps/M24_AXI" + "DDR", + "hier_ps/DDR" ] }, - "hier_ps_M29_AXI": { + "S00_AXI4_4": { "interface_ports": [ - "hier_ps/M29_AXI", - "hier_gpio_0/S00_AXI5" + "hier_gpio_3/S00_AXI4", + "hier_ps/M28_AXI" ] }, - "S00_AXI_3": { + "S00_AXI3_3": { "interface_ports": [ - "hier_gpio_1/S00_AXI", - "hier_ps/M14_AXI" + "hier_gpio_2/S00_AXI3", + "hier_ps/M22_AXI" ] }, - "S00_AXI1_2": { + "S00_AXI3_4": { "interface_ports": [ - "hier_gpio_0/S00_AXI1", - "hier_ps/M11_AXI" + "hier_gpio_3/S00_AXI3", + "hier_ps/M27_AXI" ] }, - "hier_ps_M34_AXI1": { + "S00_AXI3_1": { "interface_ports": [ - "hier_ps/M34_AXI", - "hier_gpio_2/S00_AXI6" + "hier_gpio_0/S00_AXI3", + "hier_ps/M12_AXI" ] }, - "S00_AXI_4": { + "hier_ps_M30_AXI": { "interface_ports": [ - "hier_gpio_2/S00_AXI", - "hier_ps/M19_AXI" + "hier_ps/M30_AXI", + "hier_gpio_1/S00_AXI5" ] }, - "S00_AXI4_1": { + "S00_AXI3_2": { "interface_ports": [ - "hier_gpio_0/S00_AXI4", - "hier_ps/M13_AXI" + "hier_gpio_1/S00_AXI3", + "hier_ps/M17_AXI" ] }, - "hier_ps_M32_AXI1": { + "hier_ps_M36_AXI1": { "interface_ports": [ - "hier_ps/M32_AXI", - "hier_gpio_3/S00_AXI5" + "hier_ps/M36_AXI", + "hier_gpio_1/S00_AXI6" ] }, - "hier_ps_M36_AXI": { + "hier_ps_M35_AXI1": { "interface_ports": [ - "amdc_adc_0/S00_AXI", - "hier_ps/M04_AXI" + "hier_ps/M35_AXI", + "hier_gpio_0/S00_AXI6" ] }, - "S00_AXI4_3": { + "S00_AXI1_1": { "interface_ports": [ - "hier_gpio_2/S00_AXI4", - "hier_ps/M23_AXI" + "hier_powerstack/S00_AXI1", + "hier_ps/M07_AXI" ] }, - "S00_AXI2_1": { + "S00_AXI1_4": { "interface_ports": [ - "hier_powerstack/S00_AXI2", - "hier_ps/M08_AXI" + "hier_gpio_2/S00_AXI1", + "hier_ps/M21_AXI" ] }, - "S00_AXI_2": { + "S00_AXI1_3": { "interface_ports": [ - "hier_gpio_0/S00_AXI", - "hier_ps/M09_AXI" + "hier_gpio_1/S00_AXI1", + "hier_ps/M16_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "S00_AXI4_2": { "interface_ports": [ - "FIXED_IO", - "hier_ps/FIXED_IO" + "hier_gpio_1/S00_AXI4", + "hier_ps/M18_AXI" ] } }, diff --git a/sdk/app_cpu1/common/drv/can.c b/sdk/app_cpu1/common/drv/can.c new file mode 100644 index 00000000..c98bfbd1 --- /dev/null +++ b/sdk/app_cpu1/common/drv/can.c @@ -0,0 +1,368 @@ +#include "can.h" +#include "drv/uart.h" +#include "gp3io_mux.h" +#include "sys/defines.h" +#include "xcanps.h" +#include "xparameters.h" +#include + +#define CAN0_DEVICE_ID XPAR_XCANPS_0_DEVICE_ID +#define CAN1_DEVICE_ID XPAR_XCANPS_1_DEVICE_ID + +// Maximum CAN frame length in words. +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS (XCANPS_MAX_FRAME_SIZE / sizeof(u32)) + +// Default number of bytes of data sending +#define FRAME_DATA_LENGTH 8 + +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +// Two CAN peripherals +static XCanPs CanPs0; +static XCanPs CanPs1; + +// Representing device we are currently on +static XCanPs *CanPs; + +// Set the mode of the CAN device +int can_setmode(can_mode_t mode) +{ + XCanPs *CanInstPtr = CanPs; + uint32_t currMode = XCanPs_GetMode(CanInstPtr); + if (currMode == XCANPS_MODE_LOOPBACK && mode != CAN_CONFIG) { +#ifdef CAN_DEBUG + print("\nCAN peripheral currently in loopback mode. Can only enter config mode from here."); +#endif + return FAILURE; + } else if (currMode == XCANPS_MODE_NORMAL && mode != CAN_SLEEP && mode != CAN_CONFIG) { +#ifdef CAN_DEBUG + print("\nCAN peripheral currently in normal mode. Can only enter config or sleep mode from here."); +#endif + return FAILURE; + } + + XCanPs_EnterMode(CanInstPtr, mode); + + // Wait to reach specified mode, should happen instantaneously + while (XCanPs_GetMode(CanInstPtr) != mode) + ; + return SUCCESS; +} + +// Set Baud Rate Prescalar Register (BRPR) +int can_setbaud(int rate) +{ + int Status; + XCanPs *CanInstPtr = CanPs; + + // Ensure CAN peripheral in config mode + if (XCanPs_GetMode(CanInstPtr) != XCANPS_MODE_CONFIG) { +#ifdef CAN_DEBUG + print("\nMust be in config mode to set baud rate prescalar register"); +#endif + return FAILURE; + } + + Status = XCanPs_SetBaudRatePrescaler(CanInstPtr, rate); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Set Bit Timing Register (BTR) +int can_set_btr(uint8_t sjw, uint8_t ts2, uint8_t ts1) +{ + int Status; + XCanPs *CanInstPtr = CanPs; + + // Ensure CAN peripheral in config mode + if (XCanPs_GetMode(CanInstPtr) != XCANPS_MODE_CONFIG) { +#ifdef CAN_DEBUG + print("\nMust be in config mode to set bit timing register"); +#endif + return FAILURE; + } + + Status = XCanPs_SetBitTiming(CanInstPtr, sjw, ts2, ts1); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Set CAN peripheral that we are using currently +int can_set_peripheral(int device_id) +{ + if (device_id != 1 && device_id != 0) + return FAILURE; + else if (device_id) + CanPs = &CanPs1; + else + CanPs = &CanPs0; + return SUCCESS; +} + +// Initialize the CAN device, default settings +int can_init(int device_id) +{ + + // Set GPIO Device and Port + gp3io_mux_set_device(GP3IO_MUX_1_BASE_ADDR, GP3IO_MUX_DEVICE1); + + XCanPs *CanInstPtr; + u16 DeviceId; + + // Initialize the user specified CAN peripheral + if (device_id != 1 && device_id != 0) { +#ifdef CAN_DEBUG + printf("device_id can only be 0 or 1\n"); +#endif + return FAILURE; + } else if (!device_id) { + DeviceId = CAN0_DEVICE_ID; + CanInstPtr = &CanPs0; + CanPs = &CanPs0; + printf("CAN0:\tInitializing...\n"); + } else { + DeviceId = CAN1_DEVICE_ID; + CanInstPtr = &CanPs1; + CanPs = &CanPs1; + printf("CAN1:\tInitializing...\n"); + } + + int Status; + XCanPs_Config *Config; + + // Initialize the CAN driver so that it's ready to use + // Look up the configuration in the config table, then initialize it + Config = XCanPs_LookupConfig(DeviceId); + if (Config == NULL || CanInstPtr == NULL) { + return FAILURE; + } + + Status = XCanPs_CfgInitialize(CanInstPtr, Config, Config->BaseAddr); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Run self-test on the device, which verifies basic sanity of the + // device and the driver + Status = XCanPs_SelfTest(CanInstPtr); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Enter Configuration Mode so that we can setup Baud Rate Precalar + // Register (BRPR) and Bit Timing Register (BTR). + Status = can_setmode(XCANPS_MODE_CONFIG); + if (Status != SUCCESS) + return FAILURE; + + // Set Baud Rate Prescalar Register (BRPR) and + // Bit Timing Register (BTR) + Status = can_setbaud(DEFAULT_BAUD_PRESCALAR); + if (Status != SUCCESS) { + return FAILURE; + } + Status = can_set_btr(DEFAULT_BTR_SYNCJUMPWIDTH, DEFAULT_BTR_SECOND_TIMESEGMENT, DEFAULT_BTR_FIRST_TIMESEGMENT); + + if (Status != SUCCESS) { + return FAILURE; + } + + // Enter Normal Mode to use CAN peripheral + return can_setmode(XCANPS_MODE_NORMAL); +} + +// Send a CAN packet +int can_send(can_packet_t *packet, uint32_t num_bytes) +{ + u8 *FramePtr; + int i; + int Status; + XCanPs *CanInstPtr = CanPs; + + // Check that pointer isn't NULL + if (packet == NULL) { +#ifdef CAN_DEBUG + printf("Packet of data is null, please initialize it!\n"); +#endif + return FAILURE; + } + + // Check number of bytes user is sending at once is between 1 to 8 + if (num_bytes <= 0 || num_bytes > 8) { +#ifdef CAN_DEBUG + printf("Can only send 8 bytes at once!\n"); +#endif + return FAILURE; + } + + // Populate correct values for Identifier - check Zync 700 Reference Manual for meaning of this info + TxFrame[0] = (u32) XCanPs_CreateIdValue((u32) packet->message_id, 0, 0, 0, 0); + + // Specify number of bytes of data sending + TxFrame[1] = (u32) XCanPs_CreateDlcValue((u32) packet->num_bytes); + + // Populate the TX FIFO with CAN packet to send + FramePtr = (u8 *) (&TxFrame[2]); + for (i = 0; i < packet->num_bytes; i++) { + *FramePtr++ = (u8) packet->buffer[i]; + } + + // Check if TxFIFO is full + if (XCanPs_IsTxFifoFull(CanInstPtr) == TRUE) { +#ifdef CAN_DEBUG + printf("CAN TxFIFO is full, try sending your data again in a bit!\n"); +#endif + return FAILURE; + } + + // Send the frame + Status = XCanPs_Send(CanInstPtr, TxFrame); + + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} + +// Print latest can packet received +int can_rcv(can_packet_t *packet) +{ + u8 *FramePtr; + int Status; + int i; + + XCanPs *CanInstPtr = CanPs; + + // Check if a frame is empty + if (XCanPs_IsRxEmpty(CanInstPtr) == TRUE) { +#ifdef CAN_DEBUG + printf("Currently there isn't a packet in the RxFIFO, try again in a bit!\n"); +#endif + return FAILURE; + } + + // Receive a frame and verify its contents + Status = XCanPs_Recv(CanInstPtr, RxFrame); + + if (Status == XST_SUCCESS) { + packet->message_id = (int) (RxFrame[0] >> 21); + packet->num_bytes = (int) (RxFrame[1] >> 28); + FramePtr = (u8 *) (&RxFrame[2]); + for (i = 0; i < packet->num_bytes; i++) { + packet->buffer[i] = *FramePtr; + FramePtr++; + } + return SUCCESS; + } + return FAILURE; +} + +// Print mode the CAN peripheral is in, useful for debugging purposes +void can_print_mode() +{ +#ifdef CAN_DEBUG + XCanPs *CanInstPtr = CanPs; + + uint32_t mode; + mode = XCanPs_GetMode(CanInstPtr); + if (mode == XCANPS_MODE_NORMAL) + print("\nXCANPS_MODE_NORMAL"); + else if (mode == XCANPS_MODE_LOOPBACK) + print("\nXCANPS_MODE_LOOPBACK"); + else if (mode == XCANPS_MODE_CONFIG) + print("\nXCANPS_MODE_CONFIG"); + else if (mode == XCANPS_MODE_SLEEP) + print("\nXCANPS_MODE_SLEEP"); + else + print("\nOther mode"); +#endif +} + +// Print the CAN peripheral the user has set, useful for debugging purposes +void can_print_peripheral() +{ +#ifdef CAN_DEBUG + if (CanPs == &CanPs0) + print("\nCAN 0"); + else if (CanPs == &CanPs1) + print("\nCAN 1"); + else + print("\nCAN peripheral not set properly"); +#endif +} + +// Check packet received in loopback mode is correct +static int can_checkpacket() +{ + u8 *FramePtr; + int Status; + int Index; + + XCanPs *CanInstPtr = CanPs; + + // Wait until a frame is received + while (XCanPs_IsRxEmpty(CanInstPtr) == TRUE) + ; + + // Receive a frame and verify its contents + Status = XCanPs_Recv(CanInstPtr, RxFrame); + if (Status == XST_SUCCESS) { + // Verify Identifier and Data Length Code + if (RxFrame[0] != (u32) XCanPs_CreateIdValue((u32) DEFAULT_CAN_MESSAGE_ID, 0, 0, 0, 0)) + return XST_LOOPBACK_ERROR; + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) + return XST_LOOPBACK_ERROR; + + // Verify Data field contents + FramePtr = (u8 *) (&RxFrame[2]); + for (Index = 0; Index < FRAME_DATA_LENGTH; Index++) { + if (*FramePtr++ != (u8) Index) { + return XST_LOOPBACK_ERROR; + } + } + } + + return Status; +} + +// Run a sanity check loopback test +int can_loopback_test() +{ + + int Status; + uint8_t packet[FRAME_DATA_LENGTH]; + + // Check we are in loopback mode + uint32_t mode; + XCanPs *CanInstPtr = CanPs; + mode = XCanPs_GetMode(CanInstPtr); + if (mode != XCANPS_MODE_LOOPBACK) { +#ifdef CAN_DEBUG + print("\nNot in loopback mode, can't run self test"); +#endif + return FAILURE; + } + + // Populate CAN packet + int i; + for (i = 0; i < FRAME_DATA_LENGTH; i++) { + packet[i] = i; + } + + // Send fake packet of data + Status = can_send(packet, FRAME_DATA_LENGTH); + if (Status != XST_SUCCESS) { + return FAILURE; + } + + // Check fake packet of data is received correctly + Status = can_checkpacket(); + if (Status != XST_SUCCESS) + return FAILURE; + return SUCCESS; +} diff --git a/sdk/app_cpu1/common/drv/can.h b/sdk/app_cpu1/common/drv/can.h new file mode 100644 index 00000000..52d7bc06 --- /dev/null +++ b/sdk/app_cpu1/common/drv/can.h @@ -0,0 +1,79 @@ +#ifndef CAN_H +#define CAN_H + +#include "xcanps.h" +#include + +/* + * The Baud Rate Prescaler Register (BRPR) and Bit Timing Register (BTR) + * are setup such that CAN baud rate equals 500 Kbps, assuming that the + * the CAN clock is 200 MHz. The user needs to modify these values based on + * the desired baud rate and the CAN clock frequency. For more information + * see the CAN 2.0A, CAN 2.0B, ISO 11898-1 specifications. + */ + +/* + * Timing parameters to be set in the Bit Timing Register (BTR). + * These values are for a 500 Kbps baudrate assuming the CAN input clock frequency + * is 24 MHz. + * + * The value of BTR register after using these defaults is 0x1C. According to the Zynq-7000 + * Reference Manual, the actual value is one more than the value written to the register. + * Thus, we write a value of 12 and 1 for the first and second time segment, respectively, + * to have an actual value of 13 and 2. + */ +#define DEFAULT_BTR_SYNCJUMPWIDTH 3 +#define DEFAULT_BTR_SECOND_TIMESEGMENT 1 +#define DEFAULT_BTR_FIRST_TIMESEGMENT 12 + +/* + * The Baud rate Prescalar value in the Baud Rate Prescaler Register (BRPR) + * needs to be set based on the input clock frequency to the CAN core and + * the desired CAN baud rate. + * This value is for a 500 Kbps baudrate assuming the CAN input clock frequency + * is 24 MHz. + * + * The value of the BRPR after using this default is 0x02. According to the Zync-7000 + * Reference Manual, the actual value is one more than the value written to the register. + * Thus, we write a value of 2 to the register, but the actual value is 3, which it should be. + */ +#define DEFAULT_BAUD_PRESCALAR 2 +#define DEFAULT_CAN_MESSAGE_ID 1 + +// Different CAN modes +typedef enum { + CAN_CONFIG = XCANPS_MODE_CONFIG, + CAN_LOOPBACK = XCANPS_MODE_LOOPBACK, + CAN_NORMAL = XCANPS_MODE_NORMAL, + CAN_SLEEP = XCANPS_MODE_SLEEP, + CAN_SNOOP = XCANPS_MODE_SNOOP, +} can_mode_t; + +// Struct representing an entire CAN Packet +typedef struct can_packets_t { + int message_id; + int num_bytes; + uint8_t buffer[8]; +} can_packet_t; + +// Setter methods, useful for configuring the CAN peripheral +int can_setmode(can_mode_t MODE); +int can_setbaud(int rate); +int can_set_btr(uint8_t sjw, uint8_t ts1, uint8_t ts2); +int can_set_peripheral(int device_id); + +// Initialize the CAN peripheral +int can_init(int device_id); + +// Send and get CAN packets +int can_send(can_packet_t *packet, uint32_t num_bytes); +int can_rcv(can_packet_t *packet); + +// Useful debugging functionality +void can_print_mode(); +void can_print_peripheral(); + +// Sanity check that hardware working +int can_loopback_test(); + +#endif // CAN_H From 7d29e9ca385b66bb10f9a2b0451e4e00aeafd0fd Mon Sep 17 00:00:00 2001 From: Mohamed-dek Mohamed Date: Wed, 26 Feb 2025 10:13:23 -0600 Subject: [PATCH 2/6] fixes to driver to initialize CAN and add most command functionality to CAN app --- sdk/app_cpu1/common/drv/can.c | 66 +++++++++++++++++++++++++---------- sdk/app_cpu1/common/drv/can.h | 4 +-- 2 files changed, 50 insertions(+), 20 deletions(-) diff --git a/sdk/app_cpu1/common/drv/can.c b/sdk/app_cpu1/common/drv/can.c index c98bfbd1..0901b3b3 100644 --- a/sdk/app_cpu1/common/drv/can.c +++ b/sdk/app_cpu1/common/drv/can.c @@ -177,20 +177,45 @@ int can_init(int device_id) } // Send a CAN packet -int can_send(can_packet_t *packet, uint32_t num_bytes) +int can_send(uint8_t data[8], uint32_t num_bytes) { u8 *FramePtr; int i; int Status; XCanPs *CanInstPtr = CanPs; - // Check that pointer isn't NULL - if (packet == NULL) { -#ifdef CAN_DEBUG - printf("Packet of data is null, please initialize it!\n"); -#endif - return FAILURE; - } + can_packet_t packet; + packet.message_id = 1; + packet.num_bytes = num_bytes; + for (i = 0; i < num_bytes; i++) { + packet.buffer[i] = data[i]; + } +// +// // Check that pointer isn't NULL +// if (packet == NULL) { +//#ifdef CAN_DEBUG +// printf("\nPacket of data is null, please initialize it!\n"); +// printf("%d\n", packet->message_id); +// printf("%d\n", packet->num_bytes); +// for (i = 0; i < 4; i++) { +// printf("%d", i); +// printf("%d: %u ", i, packet->buffer[i]); +// } +// printf("\n"); +// for (i = 0; i < packet->num_bytes; i++) { +// printf("%d: %u ", i, data[i]); +// } +// printf("\n"); +//#endif +// return FAILURE; +// } + + printf("\n%d\n", packet.message_id); + printf("%d\n", packet.num_bytes); + for (i = 0; i < 8; i++) { + printf("%u ", packet.buffer[i]); + } + printf("\n"); // Check number of bytes user is sending at once is between 1 to 8 if (num_bytes <= 0 || num_bytes > 8) { @@ -201,15 +226,16 @@ int can_send(can_packet_t *packet, uint32_t num_bytes) } // Populate correct values for Identifier - check Zync 700 Reference Manual for meaning of this info - TxFrame[0] = (u32) XCanPs_CreateIdValue((u32) packet->message_id, 0, 0, 0, 0); + TxFrame[0] = (u32) XCanPs_CreateIdValue((u32) packet.message_id, 0, 0, 0, 0); // Specify number of bytes of data sending - TxFrame[1] = (u32) XCanPs_CreateDlcValue((u32) packet->num_bytes); + TxFrame[1] = (u32) XCanPs_CreateDlcValue((u32) packet.num_bytes); // Populate the TX FIFO with CAN packet to send FramePtr = (u8 *) (&TxFrame[2]); - for (i = 0; i < packet->num_bytes; i++) { - *FramePtr++ = (u8) packet->buffer[i]; + for (i = 0; i < packet.num_bytes; i++) { + *FramePtr = (u8) packet.buffer[i]; + FramePtr++; } // Check if TxFIFO is full @@ -229,7 +255,7 @@ int can_send(can_packet_t *packet, uint32_t num_bytes) } // Print latest can packet received -int can_rcv(can_packet_t *packet) +int can_rcv(uint8_t buffer[8]) { u8 *FramePtr; int Status; @@ -247,13 +273,17 @@ int can_rcv(can_packet_t *packet) // Receive a frame and verify its contents Status = XCanPs_Recv(CanInstPtr, RxFrame); - + can_packet_t packet; + for (i = 0; i < 8; i++) { + packet.buffer[i] = 0; + } if (Status == XST_SUCCESS) { - packet->message_id = (int) (RxFrame[0] >> 21); - packet->num_bytes = (int) (RxFrame[1] >> 28); + packet.message_id = (int) (RxFrame[0] >> 21); + packet.num_bytes = (int) (RxFrame[1] >> 28); FramePtr = (u8 *) (&RxFrame[2]); - for (i = 0; i < packet->num_bytes; i++) { - packet->buffer[i] = *FramePtr; + for (i = 0; i < packet.num_bytes; i++) { + packet.buffer[i] = *FramePtr; + buffer[i] = packet.buffer[i]; FramePtr++; } return SUCCESS; diff --git a/sdk/app_cpu1/common/drv/can.h b/sdk/app_cpu1/common/drv/can.h index 52d7bc06..30d2ca77 100644 --- a/sdk/app_cpu1/common/drv/can.h +++ b/sdk/app_cpu1/common/drv/can.h @@ -66,8 +66,8 @@ int can_set_peripheral(int device_id); int can_init(int device_id); // Send and get CAN packets -int can_send(can_packet_t *packet, uint32_t num_bytes); -int can_rcv(can_packet_t *packet); +int can_send(uint8_t data[8], uint32_t num_bytes); +int can_rcv(uint8_t buffer[8]); // Useful debugging functionality void can_print_mode(); From d42aef24d8ef5c3f3cdce9e3b83d6292bd1818ee Mon Sep 17 00:00:00 2001 From: Mohamed-dek Mohamed Date: Wed, 26 Feb 2025 10:55:04 -0600 Subject: [PATCH 3/6] removes unneccesary comments --- sdk/app_cpu1/common/drv/can.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/sdk/app_cpu1/common/drv/can.c b/sdk/app_cpu1/common/drv/can.c index 0901b3b3..3b3aee60 100644 --- a/sdk/app_cpu1/common/drv/can.c +++ b/sdk/app_cpu1/common/drv/can.c @@ -190,25 +190,6 @@ int can_send(uint8_t data[8], uint32_t num_bytes) for (i = 0; i < num_bytes; i++) { packet.buffer[i] = data[i]; } -// -// // Check that pointer isn't NULL -// if (packet == NULL) { -//#ifdef CAN_DEBUG -// printf("\nPacket of data is null, please initialize it!\n"); -// printf("%d\n", packet->message_id); -// printf("%d\n", packet->num_bytes); -// for (i = 0; i < 4; i++) { -// printf("%d", i); -// printf("%d: %u ", i, packet->buffer[i]); -// } -// printf("\n"); -// for (i = 0; i < packet->num_bytes; i++) { -// printf("%d: %u ", i, data[i]); -// } -// printf("\n"); -//#endif -// return FAILURE; -// } printf("\n%d\n", packet.message_id); printf("%d\n", packet.num_bytes); From 09c5489b2bcbd34da19c29be21bbef1dfb5e7328 Mon Sep 17 00:00:00 2001 From: Mohamed-dek Mohamed Date: Tue, 22 Apr 2025 15:36:26 -0500 Subject: [PATCH 4/6] added CAN to GPIO4 --- hw/amdc_revf.bd | 1372 ++++++++++++++++----------- sdk/app_cpu1/common/drv/can.c | 21 +- sdk/app_cpu1/common/drv/can.h | 3 +- sdk/app_cpu1/user/.cproject | 25 +- sdk/app_cpu1/user/.project | 7 + sdk/app_cpu1/user/usr/user_apps.c | 52 - sdk/app_cpu1/user/usr/user_apps.h | 6 - sdk/app_cpu1/user/usr/user_config.h | 60 -- 8 files changed, 836 insertions(+), 710 deletions(-) delete mode 100644 sdk/app_cpu1/user/usr/user_apps.c delete mode 100644 sdk/app_cpu1/user/usr/user_apps.h delete mode 100644 sdk/app_cpu1/user/usr/user_config.h diff --git a/hw/amdc_revf.bd b/hw/amdc_revf.bd index 5c21e46f..f08c7e22 100644 --- a/hw/amdc_revf.bd +++ b/hw/amdc_revf.bd @@ -210,7 +210,13 @@ "xlconcat_2": "", "xlconstant_3": "", "amdc_eddy_current_se_0": "", - "amdc_amds_0": "" + "amdc_amds_0": "", + "xlconcat_0": "", + "xlconstant_1": "", + "xlslice_4": "", + "xlslice_5": "", + "NOT_gate_1": "", + "NOT_gate_0": "" }, "xlconcat_0": "", "xlconstant_0": "", @@ -818,6 +824,18 @@ "direction": "I", "left": "15", "right": "0" + }, + "CAN0_TX": { + "direction": "O" + }, + "CAN0_RX": { + "direction": "I" + }, + "CAN1_RX": { + "direction": "I" + }, + "CAN1_TX": { + "direction": "O" } }, "components": { @@ -901,7 +919,7 @@ "value": "667" }, "PCW_CAN0_CAN0_IO": { - "value": "MIO 30 .. 31" + "value": "EMIO" }, "PCW_CAN0_GRP_CLK_ENABLE": { "value": "0" @@ -910,7 +928,7 @@ "value": "1" }, "PCW_CAN1_CAN1_IO": { - "value": "MIO 32 .. 33" + "value": "EMIO" }, "PCW_CAN1_GRP_CLK_ENABLE": { "value": "0" @@ -1009,10 +1027,10 @@ "value": "1" }, "PCW_EN_EMIO_CAN0": { - "value": "0" + "value": "1" }, "PCW_EN_EMIO_CAN1": { - "value": "0" + "value": "1" }, "PCW_EN_EMIO_CD_SDIO1": { "value": "1" @@ -1582,16 +1600,16 @@ "value": "54" }, "PCW_MIO_TREE_PERIPHERALS": { - "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#CAN 0#CAN 0#CAN 1#CAN 1#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0" + "value": "GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#GPIO#GPIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0" }, "PCW_MIO_TREE_SIGNALS": { - "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#rx#tx#tx#rx#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#rx#tx#mdc#mdio" + "value": "gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#gpio[8]#gpio[9]#data[0]#cmd#clk#data[1]#data[2]#data[3]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#gpio[40]#gpio[41]#gpio[42]#gpio[43]#gpio[44]#gpio[45]#gpio[46]#gpio[47]#gpio[48]#gpio[49]#rx#tx#mdc#mdio" }, "PCW_P2F_CAN0_INTR": { - "value": "1" + "value": "0" }, "PCW_P2F_CAN1_INTR": { - "value": "1" + "value": "0" }, "PCW_P2F_UART0_INTR": { "value": "1" @@ -3085,10 +3103,10 @@ } }, "interface_nets": { - "s00_data_fifo_to_s00_couplers": { + "auto_pc_to_s00_data_fifo": { "interface_ports": [ - "M_AXI", - "s00_data_fifo/M_AXI" + "s00_data_fifo/S_AXI", + "auto_pc/M_AXI" ] }, "s00_couplers_to_auto_pc": { @@ -3097,10 +3115,10 @@ "auto_pc/S_AXI" ] }, - "auto_pc_to_s00_data_fifo": { + "s00_data_fifo_to_s00_couplers": { "interface_ports": [ - "s00_data_fifo/S_AXI", - "auto_pc/M_AXI" + "M_AXI", + "s00_data_fifo/M_AXI" ] } }, @@ -3563,17 +3581,17 @@ } }, "interface_nets": { - "auto_pc_to_m05_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m05_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m05_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -3739,17 +3757,17 @@ } }, "interface_nets": { - "auto_pc_to_m07_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m07_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m07_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4233,17 +4251,17 @@ } }, "interface_nets": { - "m13_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m13_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m13_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4321,17 +4339,17 @@ } }, "interface_nets": { - "m14_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m14_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m14_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -4727,17 +4745,17 @@ } }, "interface_nets": { - "auto_pc_to_m19_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m19_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m19_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4869,17 +4887,17 @@ } }, "interface_nets": { - "auto_pc_to_m21_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m21_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m21_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4957,17 +4975,17 @@ } }, "interface_nets": { - "auto_pc_to_m22_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m22_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m22_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5045,17 +5063,17 @@ } }, "interface_nets": { - "m23_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m23_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m23_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5133,17 +5151,17 @@ } }, "interface_nets": { - "m24_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m24_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m24_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5275,17 +5293,17 @@ } }, "interface_nets": { - "m26_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m26_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m26_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5363,17 +5381,17 @@ } }, "interface_nets": { - "m27_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m27_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m27_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5627,17 +5645,17 @@ } }, "interface_nets": { - "auto_pc_to_m30_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m30_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m30_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -6069,214 +6087,100 @@ } }, "interface_nets": { - "xbar_to_i00_couplers": { + "m22_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M00_AXI", - "i00_couplers/S_AXI" + "M22_AXI", + "m22_couplers/M_AXI" ] }, - "i00_couplers_to_tier2_xbar_0": { + "tier2_xbar_2_to_m21_couplers": { "interface_ports": [ - "i00_couplers/M_AXI", - "tier2_xbar_0/S00_AXI" + "tier2_xbar_2/M05_AXI", + "m21_couplers/S_AXI" ] }, - "xbar_to_i01_couplers": { + "m23_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "xbar/M01_AXI", - "i01_couplers/S_AXI" + "M23_AXI", + "m23_couplers/M_AXI" ] }, - "xbar_to_i02_couplers": { + "tier2_xbar_2_to_m22_couplers": { "interface_ports": [ - "xbar/M02_AXI", - "i02_couplers/S_AXI" + "tier2_xbar_2/M06_AXI", + "m22_couplers/S_AXI" ] }, - "i01_couplers_to_tier2_xbar_1": { + "m24_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i01_couplers/M_AXI", - "tier2_xbar_1/S00_AXI" + "M24_AXI", + "m24_couplers/M_AXI" ] }, - "i02_couplers_to_tier2_xbar_2": { + "tier2_xbar_2_to_m23_couplers": { "interface_ports": [ - "i02_couplers/M_AXI", - "tier2_xbar_2/S00_AXI" + "tier2_xbar_2/M07_AXI", + "m23_couplers/S_AXI" ] }, - "xbar_to_i03_couplers": { + "tier2_xbar_3_to_m24_couplers": { "interface_ports": [ - "xbar/M03_AXI", - "i03_couplers/S_AXI" + "tier2_xbar_3/M00_AXI", + "m24_couplers/S_AXI" ] }, - "i03_couplers_to_tier2_xbar_3": { + "m25_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "i03_couplers/M_AXI", - "tier2_xbar_3/S00_AXI" + "M25_AXI", + "m25_couplers/M_AXI" ] }, - "xbar_to_i04_couplers": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ - "xbar/M04_AXI", - "i04_couplers/S_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, - "i04_couplers_to_tier2_xbar_4": { + "s00_couplers_to_xbar": { "interface_ports": [ - "i04_couplers/M_AXI", - "tier2_xbar_4/S00_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] }, - "m31_couplers_to_ps7_0_axi_periph": { + "m00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M31_AXI", - "m31_couplers/M_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m13_couplers": { + "tier2_xbar_0_to_m00_couplers": { "interface_ports": [ - "tier2_xbar_1/M05_AXI", - "m13_couplers/S_AXI" + "tier2_xbar_0/M00_AXI", + "m00_couplers/S_AXI" ] }, - "m14_couplers_to_ps7_0_axi_periph": { + "m01_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M14_AXI", - "m14_couplers/M_AXI" + "M01_AXI", + "m01_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m14_couplers": { + "m02_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M06_AXI", - "m14_couplers/S_AXI" - ] - }, - "m15_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M15_AXI", - "m15_couplers/M_AXI" - ] - }, - "tier2_xbar_1_to_m15_couplers": { - "interface_ports": [ - "tier2_xbar_1/M07_AXI", - "m15_couplers/S_AXI" - ] - }, - "m16_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M16_AXI", - "m16_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m16_couplers": { - "interface_ports": [ - "tier2_xbar_2/M00_AXI", - "m16_couplers/S_AXI" - ] - }, - "m17_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M17_AXI", - "m17_couplers/M_AXI" - ] - }, - "m18_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M18_AXI", - "m18_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m17_couplers": { - "interface_ports": [ - "tier2_xbar_2/M01_AXI", - "m17_couplers/S_AXI" - ] - }, - "tier2_xbar_2_to_m18_couplers": { - "interface_ports": [ - "tier2_xbar_2/M02_AXI", - "m18_couplers/S_AXI" - ] - }, - "m19_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M19_AXI", - "m19_couplers/M_AXI" - ] - }, - "m20_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M20_AXI", - "m20_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m19_couplers": { - "interface_ports": [ - "tier2_xbar_2/M03_AXI", - "m19_couplers/S_AXI" - ] - }, - "m21_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M21_AXI", - "m21_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m20_couplers": { - "interface_ports": [ - "tier2_xbar_2/M04_AXI", - "m20_couplers/S_AXI" - ] - }, - "tier2_xbar_2_to_m21_couplers": { - "interface_ports": [ - "tier2_xbar_2/M05_AXI", - "m21_couplers/S_AXI" - ] - }, - "m22_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M22_AXI", - "m22_couplers/M_AXI" - ] - }, - "m23_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M23_AXI", - "m23_couplers/M_AXI" - ] - }, - "tier2_xbar_2_to_m22_couplers": { - "interface_ports": [ - "tier2_xbar_2/M06_AXI", - "m22_couplers/S_AXI" - ] - }, - "tier2_xbar_2_to_m23_couplers": { - "interface_ports": [ - "tier2_xbar_2/M07_AXI", - "m23_couplers/S_AXI" - ] - }, - "m24_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M24_AXI", - "m24_couplers/M_AXI" + "M02_AXI", + "m02_couplers/M_AXI" ] }, - "m25_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m01_couplers": { "interface_ports": [ - "M25_AXI", - "m25_couplers/M_AXI" + "tier2_xbar_0/M01_AXI", + "m01_couplers/S_AXI" ] }, - "tier2_xbar_3_to_m24_couplers": { + "m26_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_3/M00_AXI", - "m24_couplers/S_AXI" + "M26_AXI", + "m26_couplers/M_AXI" ] }, "tier2_xbar_3_to_m25_couplers": { @@ -6285,12 +6189,6 @@ "m25_couplers/S_AXI" ] }, - "m26_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M26_AXI", - "m26_couplers/M_AXI" - ] - }, "tier2_xbar_3_to_m26_couplers": { "interface_ports": [ "tier2_xbar_3/M02_AXI", @@ -6303,10 +6201,10 @@ "m27_couplers/M_AXI" ] }, - "m28_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m37_couplers": { "interface_ports": [ - "M28_AXI", - "m28_couplers/M_AXI" + "tier2_xbar_4/M05_AXI", + "m37_couplers/S_AXI" ] }, "tier2_xbar_3_to_m27_couplers": { @@ -6315,6 +6213,12 @@ "m27_couplers/S_AXI" ] }, + "m28_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M28_AXI", + "m28_couplers/M_AXI" + ] + }, "m29_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M29_AXI", @@ -6327,28 +6231,28 @@ "m28_couplers/S_AXI" ] }, - "m30_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M30_AXI", - "m30_couplers/M_AXI" - ] - }, "tier2_xbar_3_to_m29_couplers": { "interface_ports": [ "tier2_xbar_3/M05_AXI", "m29_couplers/S_AXI" ] }, + "m30_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M30_AXI", + "m30_couplers/M_AXI" + ] + }, "tier2_xbar_3_to_m30_couplers": { "interface_ports": [ "tier2_xbar_3/M06_AXI", "m30_couplers/S_AXI" ] }, - "m32_couplers_to_ps7_0_axi_periph": { + "m31_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M32_AXI", - "m32_couplers/M_AXI" + "M31_AXI", + "m31_couplers/M_AXI" ] }, "tier2_xbar_3_to_m31_couplers": { @@ -6357,10 +6261,10 @@ "m31_couplers/S_AXI" ] }, - "tier2_xbar_4_to_m32_couplers": { + "m32_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_4/M00_AXI", - "m32_couplers/S_AXI" + "M32_AXI", + "m32_couplers/M_AXI" ] }, "m33_couplers_to_ps7_0_axi_periph": { @@ -6369,10 +6273,10 @@ "m33_couplers/M_AXI" ] }, - "m34_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_4_to_m32_couplers": { "interface_ports": [ - "M34_AXI", - "m34_couplers/M_AXI" + "tier2_xbar_4/M00_AXI", + "m32_couplers/S_AXI" ] }, "tier2_xbar_4_to_m33_couplers": { @@ -6381,6 +6285,12 @@ "m33_couplers/S_AXI" ] }, + "m34_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M34_AXI", + "m34_couplers/M_AXI" + ] + }, "tier2_xbar_4_to_m34_couplers": { "interface_ports": [ "tier2_xbar_4/M02_AXI", @@ -6417,52 +6327,64 @@ "m37_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m37_couplers": { + "xbar_to_i00_couplers": { "interface_ports": [ - "tier2_xbar_4/M05_AXI", - "m37_couplers/S_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "ps7_0_axi_periph_to_s00_couplers": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "m00_couplers_to_ps7_0_axi_periph": { + "xbar_to_i01_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "xbar_to_i02_couplers": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "xbar/M02_AXI", + "i02_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m00_couplers": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "tier2_xbar_0/M00_AXI", - "m00_couplers/S_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "m01_couplers_to_ps7_0_axi_periph": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "M01_AXI", - "m01_couplers/M_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, - "tier2_xbar_0_to_m01_couplers": { + "xbar_to_i03_couplers": { "interface_ports": [ - "tier2_xbar_0/M01_AXI", - "m01_couplers/S_AXI" + "xbar/M03_AXI", + "i03_couplers/S_AXI" ] }, - "m02_couplers_to_ps7_0_axi_periph": { + "xbar_to_i04_couplers": { "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" + "xbar/M04_AXI", + "i04_couplers/S_AXI" + ] + }, + "i03_couplers_to_tier2_xbar_3": { + "interface_ports": [ + "i03_couplers/M_AXI", + "tier2_xbar_3/S00_AXI" + ] + }, + "i04_couplers_to_tier2_xbar_4": { + "interface_ports": [ + "i04_couplers/M_AXI", + "tier2_xbar_4/S00_AXI" ] }, "m03_couplers_to_ps7_0_axi_periph": { @@ -6477,18 +6399,18 @@ "m02_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m03_couplers": { - "interface_ports": [ - "tier2_xbar_0/M03_AXI", - "m03_couplers/S_AXI" - ] - }, "m04_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M04_AXI", "m04_couplers/M_AXI" ] }, + "tier2_xbar_0_to_m03_couplers": { + "interface_ports": [ + "tier2_xbar_0/M03_AXI", + "m03_couplers/S_AXI" + ] + }, "tier2_xbar_0_to_m04_couplers": { "interface_ports": [ "tier2_xbar_0/M04_AXI", @@ -6513,22 +6435,16 @@ "m06_couplers/M_AXI" ] }, - "m07_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" - ] - }, "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ "tier2_xbar_0/M06_AXI", "m06_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m07_couplers": { + "m07_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M07_AXI", - "m07_couplers/S_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, "m08_couplers_to_ps7_0_axi_periph": { @@ -6537,10 +6453,10 @@ "m08_couplers/M_AXI" ] }, - "m09_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" ] }, "tier2_xbar_1_to_m08_couplers": { @@ -6549,10 +6465,10 @@ "m08_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m09_couplers": { + "m09_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_1/M01_AXI", - "m09_couplers/S_AXI" + "M09_AXI", + "m09_couplers/M_AXI" ] }, "m10_couplers_to_ps7_0_axi_periph": { @@ -6561,10 +6477,10 @@ "m10_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m10_couplers": { + "tier2_xbar_1_to_m09_couplers": { "interface_ports": [ - "tier2_xbar_1/M02_AXI", - "m10_couplers/S_AXI" + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" ] }, "m11_couplers_to_ps7_0_axi_periph": { @@ -6573,6 +6489,12 @@ "m11_couplers/M_AXI" ] }, + "tier2_xbar_1_to_m10_couplers": { + "interface_ports": [ + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" + ] + }, "m12_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M12_AXI", @@ -6585,16 +6507,112 @@ "m11_couplers/S_AXI" ] }, + "m13_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M13_AXI", + "m13_couplers/M_AXI" + ] + }, "tier2_xbar_1_to_m12_couplers": { "interface_ports": [ "tier2_xbar_1/M04_AXI", "m12_couplers/S_AXI" ] }, - "m13_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_1_to_m13_couplers": { "interface_ports": [ - "M13_AXI", - "m13_couplers/M_AXI" + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" + ] + }, + "m14_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M14_AXI", + "m14_couplers/M_AXI" + ] + }, + "m15_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M15_AXI", + "m15_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m14_couplers": { + "interface_ports": [ + "tier2_xbar_1/M06_AXI", + "m14_couplers/S_AXI" + ] + }, + "m16_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M16_AXI", + "m16_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m15_couplers": { + "interface_ports": [ + "tier2_xbar_1/M07_AXI", + "m15_couplers/S_AXI" + ] + }, + "tier2_xbar_2_to_m16_couplers": { + "interface_ports": [ + "tier2_xbar_2/M00_AXI", + "m16_couplers/S_AXI" + ] + }, + "m17_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M17_AXI", + "m17_couplers/M_AXI" + ] + }, + "m18_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M18_AXI", + "m18_couplers/M_AXI" + ] + }, + "tier2_xbar_2_to_m17_couplers": { + "interface_ports": [ + "tier2_xbar_2/M01_AXI", + "m17_couplers/S_AXI" + ] + }, + "tier2_xbar_2_to_m18_couplers": { + "interface_ports": [ + "tier2_xbar_2/M02_AXI", + "m18_couplers/S_AXI" + ] + }, + "m19_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M19_AXI", + "m19_couplers/M_AXI" + ] + }, + "tier2_xbar_2_to_m19_couplers": { + "interface_ports": [ + "tier2_xbar_2/M03_AXI", + "m19_couplers/S_AXI" + ] + }, + "m20_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M20_AXI", + "m20_couplers/M_AXI" + ] + }, + "tier2_xbar_2_to_m20_couplers": { + "interface_ports": [ + "tier2_xbar_2/M04_AXI", + "m20_couplers/S_AXI" + ] + }, + "m21_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M21_AXI", + "m21_couplers/M_AXI" ] } }, @@ -7191,22 +7209,28 @@ } }, "interface_nets": { - "Conn1": { + "Conn27": { "interface_ports": [ - "M00_AXI", - "ps7_0_axi_periph/M00_AXI" + "M27_AXI", + "ps7_0_axi_periph/M27_AXI" ] }, - "Conn17": { + "Conn13": { "interface_ports": [ - "M17_AXI", - "ps7_0_axi_periph/M17_AXI" + "M12_AXI", + "ps7_0_axi_periph/M12_AXI" ] }, - "Conn22": { + "Conn1": { "interface_ports": [ - "M22_AXI", - "ps7_0_axi_periph/M22_AXI" + "M00_AXI", + "ps7_0_axi_periph/M00_AXI" + ] + }, + "Conn6": { + "interface_ports": [ + "M05_AXI", + "ps7_0_axi_periph/M05_AXI" ] }, "Conn28": { @@ -7215,10 +7239,10 @@ "ps7_0_axi_periph/M28_AXI" ] }, - "Conn23": { + "Conn17": { "interface_ports": [ - "M23_AXI", - "ps7_0_axi_periph/M23_AXI" + "M17_AXI", + "ps7_0_axi_periph/M17_AXI" ] }, "processing_system7_0_M_AXI_GP0": { @@ -7227,10 +7251,10 @@ "ps7_0_axi_periph/S00_AXI" ] }, - "Conn6": { + "Conn22": { "interface_ports": [ - "M05_AXI", - "ps7_0_axi_periph/M05_AXI" + "M22_AXI", + "ps7_0_axi_periph/M22_AXI" ] }, "Conn19": { @@ -7239,10 +7263,10 @@ "ps7_0_axi_periph/M19_AXI" ] }, - "Conn13": { + "Conn23": { "interface_ports": [ - "M12_AXI", - "ps7_0_axi_periph/M12_AXI" + "M23_AXI", + "ps7_0_axi_periph/M23_AXI" ] }, "Conn29": { @@ -7257,24 +7281,18 @@ "ps7_0_axi_periph/M08_AXI" ] }, - "Conn16": { - "interface_ports": [ - "M16_AXI", - "ps7_0_axi_periph/M16_AXI" - ] - }, - "Conn27": { - "interface_ports": [ - "M27_AXI", - "ps7_0_axi_periph/M27_AXI" - ] - }, "Conn15": { "interface_ports": [ "M15_AXI", "ps7_0_axi_periph/M15_AXI" ] }, + "Conn16": { + "interface_ports": [ + "M16_AXI", + "ps7_0_axi_periph/M16_AXI" + ] + }, "Conn12": { "interface_ports": [ "M11_AXI", @@ -7299,24 +7317,12 @@ "ps7_0_axi_periph/M37_AXI" ] }, - "Conn10": { - "interface_ports": [ - "M09_AXI", - "ps7_0_axi_periph/M09_AXI" - ] - }, "Conn18": { "interface_ports": [ "M18_AXI", "ps7_0_axi_periph/M18_AXI" ] }, - "ps7_0_axi_periph_M32_AXI": { - "interface_ports": [ - "M32_AXI", - "ps7_0_axi_periph/M32_AXI" - ] - }, "ps7_0_axi_periph_M30_AXI": { "interface_ports": [ "M30_AXI", @@ -7329,16 +7335,28 @@ "ps7_0_axi_periph/M01_AXI" ] }, + "Conn10": { + "interface_ports": [ + "M09_AXI", + "ps7_0_axi_periph/M09_AXI" + ] + }, + "ps7_0_axi_periph_M32_AXI": { + "interface_ports": [ + "M32_AXI", + "ps7_0_axi_periph/M32_AXI" + ] + }, "Conn21": { "interface_ports": [ "M21_AXI", "ps7_0_axi_periph/M21_AXI" ] }, - "Conn3": { + "Conn11": { "interface_ports": [ - "M02_AXI", - "ps7_0_axi_periph/M02_AXI" + "M10_AXI", + "ps7_0_axi_periph/M10_AXI" ] }, "processing_system7_0_FIXED_IO": { @@ -7347,16 +7365,16 @@ "processing_system7_0/FIXED_IO" ] }, - "Conn8": { + "Conn3": { "interface_ports": [ - "M07_AXI", - "ps7_0_axi_periph/M07_AXI" + "M02_AXI", + "ps7_0_axi_periph/M02_AXI" ] }, - "Conn11": { + "Conn8": { "interface_ports": [ - "M10_AXI", - "ps7_0_axi_periph/M10_AXI" + "M07_AXI", + "ps7_0_axi_periph/M07_AXI" ] }, "Conn25": { @@ -7365,24 +7383,30 @@ "ps7_0_axi_periph/M25_AXI" ] }, - "Conn14": { - "interface_ports": [ - "M14_AXI", - "ps7_0_axi_periph/M14_AXI" - ] - }, "Conn20": { "interface_ports": [ "M20_AXI", "ps7_0_axi_periph/M20_AXI" ] }, + "Conn14": { + "interface_ports": [ + "M14_AXI", + "ps7_0_axi_periph/M14_AXI" + ] + }, "Conn7": { "interface_ports": [ "M06_AXI", "ps7_0_axi_periph/M06_AXI" ] }, + "Conn5": { + "interface_ports": [ + "M04_AXI", + "ps7_0_axi_periph/M04_AXI" + ] + }, "ps7_0_axi_periph_M13_AXI": { "interface_ports": [ "M13_AXI", @@ -7395,22 +7419,16 @@ "ps7_0_axi_periph/M24_AXI" ] }, - "Conn5": { - "interface_ports": [ - "M04_AXI", - "ps7_0_axi_periph/M04_AXI" - ] - }, "Conn26": { "interface_ports": [ "M26_AXI", "ps7_0_axi_periph/M26_AXI" ] }, - "ps7_0_axi_periph_M31_AXI": { + "ps7_0_axi_periph_M29_AXI": { "interface_ports": [ - "M31_AXI", - "ps7_0_axi_periph/M31_AXI" + "M29_AXI", + "ps7_0_axi_periph/M29_AXI" ] }, "Conn4": { @@ -7419,16 +7437,10 @@ "ps7_0_axi_periph/M03_AXI" ] }, - "ps7_0_axi_periph_M29_AXI": { - "interface_ports": [ - "M29_AXI", - "ps7_0_axi_periph/M29_AXI" - ] - }, - "ps7_0_axi_periph_M35_AXI": { + "ps7_0_axi_periph_M31_AXI": { "interface_ports": [ - "M35_AXI", - "ps7_0_axi_periph/M35_AXI" + "M31_AXI", + "ps7_0_axi_periph/M31_AXI" ] }, "ps7_0_axi_periph_M34_AXI": { @@ -7436,6 +7448,12 @@ "M34_AXI", "ps7_0_axi_periph/M34_AXI" ] + }, + "ps7_0_axi_periph_M35_AXI": { + "interface_ports": [ + "M35_AXI", + "ps7_0_axi_periph/M35_AXI" + ] } }, "nets": { @@ -7549,6 +7567,30 @@ "IRQ_F2P", "processing_system7_0/IRQ_F2P" ] + }, + "processing_system7_0_CAN0_PHY_TX": { + "ports": [ + "processing_system7_0/CAN0_PHY_TX", + "CAN0_TX" + ] + }, + "processing_system7_0_CAN1_PHY_TX": { + "ports": [ + "processing_system7_0/CAN1_PHY_TX", + "CAN1_TX" + ] + }, + "CAN0_RX_1": { + "ports": [ + "CAN0_RX", + "processing_system7_0/CAN0_PHY_RX" + ] + }, + "CAN1_RX_1": { + "ports": [ + "CAN1_RX", + "processing_system7_0/CAN1_PHY_RX" + ] } } }, @@ -7678,18 +7720,18 @@ } }, "interface_nets": { - "ps7_0_axi_periph_M02_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_inverters_0/S00_AXI" - ] - }, "Conn1": { "interface_ports": [ "S00_AXI2", "amdc_inv_status_mux_0/S00_AXI" ] }, + "ps7_0_axi_periph_M02_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_inverters_0/S00_AXI" + ] + }, "ps7_0_axi_periph_M06_AXI": { "interface_ports": [ "S00_AXI1", @@ -8217,22 +8259,16 @@ } }, "interface_nets": { - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, - "S00_AXI6_1": { + "S00_AXI1_1": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" ] }, - "S00_AXI4_1": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] }, "hier_ps_M48_AXI": { @@ -8241,16 +8277,22 @@ "amdc_gp3io_mux_0/S00_AXI" ] }, - "S00_AXI1_1": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" + ] + }, + "S00_AXI4_1": { + "interface_ports": [ + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" ] } }, @@ -8291,10 +8333,10 @@ "ports": [ "xlconstant_0/dout", "amdc_gp3io_mux_0/device3_out", - "amdc_gp3io_mux_0/device5_out", "amdc_gp3io_mux_0/device6_out", "amdc_gp3io_mux_0/device7_out", - "amdc_gp3io_mux_0/device8_out" + "amdc_gp3io_mux_0/device8_out", + "amdc_gp3io_mux_0/device5_out" ] }, "amdc_eddy_current_se_0_sensor_control_out": { @@ -8740,12 +8782,6 @@ } }, "interface_nets": { - "S00_AXI6_1": { - "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" - ] - }, "S00_AXI5_1": { "interface_ports": [ "S00_AXI5", @@ -8758,6 +8794,18 @@ "hier_ild1420_0/S00_AXI" ] }, + "S00_AXI4_1": { + "interface_ports": [ + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" + ] + }, + "S00_AXI6_1": { + "interface_ports": [ + "S00_AXI6", + "amdc_amds_0/S00_AXI" + ] + }, "hier_ps_M48_AXI": { "interface_ports": [ "S00_AXI", @@ -8769,12 +8817,6 @@ "S00_AXI1", "amdc_eddy_current_se_0/S00_AXI" ] - }, - "S00_AXI4_1": { - "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" - ] } }, "nets": { @@ -9079,17 +9121,17 @@ } }, "interface_nets": { - "hier_ps_M12_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_ild1420_0/S00_AXI" - ] - }, "hier_ps_M13_AXI": { "interface_ports": [ "S00_AXI1", "amdc_ild1420_1/S00_AXI" ] + }, + "hier_ps_M12_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_ild1420_0/S00_AXI" + ] } }, "nets": { @@ -9263,10 +9305,10 @@ } }, "interface_nets": { - "S00_AXI1_1": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] }, "S00_AXI5_1": { @@ -9275,10 +9317,16 @@ "amdc_gpio_direct_0/S00_AXI" ] }, - "S00_AXI6_1": { + "S00_AXI1_1": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" + ] + }, + "hier_ps_M48_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] }, "S00_AXI3_1": { @@ -9292,12 +9340,6 @@ "S00_AXI4", "hier_ild1420_0/S00_AXI1" ] - }, - "hier_ps_M48_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" - ] } }, "nets": { @@ -9526,6 +9568,22 @@ }, "amds_done": { "direction": "O" + }, + "CAN0_TX": { + "direction": "I" + }, + "CAN1_TX": { + "direction": "I" + }, + "CAN0_RX": { + "direction": "O", + "left": "0", + "right": "0" + }, + "CAN1_RX": { + "direction": "O", + "left": "0", + "right": "0" } }, "components": { @@ -9602,17 +9660,17 @@ } }, "interface_nets": { - "hier_ps_M13_AXI": { - "interface_ports": [ - "S00_AXI1", - "amdc_ild1420_1/S00_AXI" - ] - }, "hier_ps_M12_AXI": { "interface_ports": [ "S00_AXI", "amdc_ild1420_0/S00_AXI" ] + }, + "hier_ps_M13_AXI": { + "interface_ports": [ + "S00_AXI1", + "amdc_ild1420_1/S00_AXI" + ] } }, "nets": { @@ -9771,18 +9829,106 @@ "CONST_VAL": { "value": "0" }, - "CONST_WIDTH": { - "value": "2" + "CONST_WIDTH": { + "value": "2" + } + } + }, + "amdc_eddy_current_se_0": { + "vlnv": "xilinx.com:user:amdc_eddy_current_sensor:2.0", + "xci_name": "amdc_revf_amdc_eddy_current_se_0_3" + }, + "amdc_amds_0": { + "vlnv": "xilinx.com:user:amdc_amds:1.0", + "xci_name": "amdc_revf_amdc_amds_0_3" + }, + "xlconcat_0": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "xci_name": "amdc_revf_xlconcat_0_2", + "parameters": { + "NUM_PORTS": { + "value": "3" + } + } + }, + "xlconstant_1": { + "vlnv": "xilinx.com:ip:xlconstant:1.1", + "xci_name": "amdc_revf_xlconstant_1_1", + "parameters": { + "CONST_VAL": { + "value": "0" + } + } + }, + "xlslice_4": { + "vlnv": "xilinx.com:ip:xlslice:1.0", + "xci_name": "amdc_revf_xlslice_4_2", + "parameters": { + "DIN_FROM": { + "value": "1" + }, + "DIN_TO": { + "value": "1" + }, + "DIN_WIDTH": { + "value": "3" + }, + "DOUT_WIDTH": { + "value": "1" + } + } + }, + "xlslice_5": { + "vlnv": "xilinx.com:ip:xlslice:1.0", + "xci_name": "amdc_revf_xlslice_5_0", + "parameters": { + "DIN_FROM": { + "value": "0" + }, + "DIN_TO": { + "value": "0" + }, + "DIN_WIDTH": { + "value": "3" + }, + "DOUT_WIDTH": { + "value": "1" + } + } + }, + "NOT_gate_1": { + "vlnv": "xilinx.com:module_ref:NOT_gate:1.0", + "xci_name": "amdc_revf_NOT_gate_0_3", + "reference_info": { + "ref_type": "hdl", + "ref_name": "NOT_gate", + "boundary_crc": "0x0" + }, + "ports": { + "a": { + "direction": "I" + }, + "b": { + "direction": "O" + } + } + }, + "NOT_gate_0": { + "vlnv": "xilinx.com:module_ref:NOT_gate:1.0", + "xci_name": "amdc_revf_NOT_gate_0_2", + "reference_info": { + "ref_type": "hdl", + "ref_name": "NOT_gate", + "boundary_crc": "0x0" + }, + "ports": { + "a": { + "direction": "I" + }, + "b": { + "direction": "O" } } - }, - "amdc_eddy_current_se_0": { - "vlnv": "xilinx.com:user:amdc_eddy_current_sensor:2.0", - "xci_name": "amdc_revf_amdc_eddy_current_se_0_3" - }, - "amdc_amds_0": { - "vlnv": "xilinx.com:user:amdc_amds:1.0", - "xci_name": "amdc_revf_amdc_amds_0_3" } }, "interface_nets": { @@ -9792,18 +9938,6 @@ "amdc_amds_0/S00_AXI" ] }, - "S00_AXI5_1": { - "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" - ] - }, - "S00_AXI3_1": { - "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" - ] - }, "S00_AXI4_1": { "interface_ports": [ "S00_AXI4", @@ -9821,6 +9955,18 @@ "S00_AXI1", "amdc_eddy_current_se_0/S00_AXI" ] + }, + "S00_AXI3_1": { + "interface_ports": [ + "S00_AXI3", + "hier_ild1420_0/S00_AXI" + ] + }, + "S00_AXI5_1": { + "interface_ports": [ + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" + ] } }, "nets": { @@ -9860,7 +10006,6 @@ "ports": [ "xlconstant_0/dout", "amdc_gp3io_mux_0/device3_out", - "amdc_gp3io_mux_0/device5_out", "amdc_gp3io_mux_0/device6_out", "amdc_gp3io_mux_0/device7_out", "amdc_gp3io_mux_0/device8_out" @@ -9986,6 +10131,61 @@ "amdc_amds_0/sync_adc", "xlconcat_2/In0" ] + }, + "CAN0_TX_1": { + "ports": [ + "CAN0_TX", + "xlconcat_0/In0" + ] + }, + "CAN1_TX_1": { + "ports": [ + "CAN1_TX", + "xlconcat_0/In2" + ] + }, + "xlconstant_1_dout": { + "ports": [ + "xlconstant_1/dout", + "xlconcat_0/In1" + ] + }, + "xlconcat_0_dout": { + "ports": [ + "xlconcat_0/dout", + "amdc_gp3io_mux_0/device5_out" + ] + }, + "amdc_gp3io_mux_0_device5_in": { + "ports": [ + "amdc_gp3io_mux_0/device5_in", + "xlslice_4/Din", + "xlslice_5/Din" + ] + }, + "NOT_gate_1_b": { + "ports": [ + "NOT_gate_1/b", + "CAN1_RX" + ] + }, + "xlslice_5_Dout": { + "ports": [ + "xlslice_5/Dout", + "NOT_gate_1/a" + ] + }, + "NOT_gate_0_b": { + "ports": [ + "NOT_gate_0/b", + "CAN0_RX" + ] + }, + "xlslice_4_Dout": { + "ports": [ + "xlslice_4/Dout", + "NOT_gate_0/a" + ] } } }, @@ -10024,28 +10224,22 @@ } }, "interface_nets": { - "S00_AXI4_1": { - "interface_ports": [ - "hier_gpio_0/S00_AXI4", - "hier_ps/M13_AXI" - ] - }, - "S00_AXI2_1": { + "hier_ps_M33_AXI1": { "interface_ports": [ - "hier_powerstack/S00_AXI2", - "hier_ps/M08_AXI" + "amdc_timing_manager_0/S00_AXI", + "hier_ps/M33_AXI" ] }, - "S00_AXI1_2": { + "S00_AXI_2": { "interface_ports": [ - "hier_gpio_0/S00_AXI1", - "hier_ps/M11_AXI" + "hier_gpio_0/S00_AXI", + "hier_ps/M09_AXI" ] }, - "S00_AXI_5": { + "hier_ps_M37_AXI1": { "interface_ports": [ - "hier_gpio_3/S00_AXI", - "hier_ps/M24_AXI" + "hier_ps/M37_AXI", + "hier_gpio_3/S00_AXI6" ] }, "processing_system7_0_FIXED_IO": { @@ -10060,28 +10254,28 @@ "hier_ps/M03_AXI" ] }, - "hier_ps_M29_AXI": { + "S00_AXI_1": { "interface_ports": [ - "hier_ps/M29_AXI", - "hier_gpio_0/S00_AXI5" + "hier_powerstack/S00_AXI", + "hier_ps/M06_AXI" ] }, - "hier_ps_M34_AXI1": { + "processing_system7_0_DDR": { "interface_ports": [ - "hier_ps/M34_AXI", - "hier_gpio_2/S00_AXI6" + "DDR", + "hier_ps/DDR" ] }, - "S00_AXI_2": { + "hier_ps_M36_AXI1": { "interface_ports": [ - "hier_gpio_0/S00_AXI", - "hier_ps/M09_AXI" + "hier_ps/M36_AXI", + "hier_gpio_1/S00_AXI6" ] }, - "S00_AXI_3": { + "hier_ps_M31_AXI": { "interface_ports": [ - "hier_gpio_1/S00_AXI", - "hier_ps/M14_AXI" + "hier_ps/M31_AXI", + "hier_gpio_2/S00_AXI5" ] }, "hier_ps_M36_AXI": { @@ -10090,22 +10284,10 @@ "hier_ps/M04_AXI" ] }, - "hier_ps_M37_AXI": { - "interface_ports": [ - "amdc_dac_0/S00_AXI", - "hier_ps/M05_AXI" - ] - }, - "S00_AXI1_5": { - "interface_ports": [ - "hier_gpio_3/S00_AXI1", - "hier_ps/M26_AXI" - ] - }, - "hier_ps_M37_AXI1": { + "S00_AXI1_3": { "interface_ports": [ - "hier_ps/M37_AXI", - "hier_gpio_3/S00_AXI6" + "hier_gpio_1/S00_AXI1", + "hier_ps/M16_AXI" ] }, "S00_AXI_4": { @@ -10114,46 +10296,46 @@ "hier_ps/M19_AXI" ] }, - "hier_ps_M32_AXI1": { + "hier_ps_M37_AXI": { "interface_ports": [ - "hier_ps/M32_AXI", - "hier_gpio_3/S00_AXI5" + "amdc_dac_0/S00_AXI", + "hier_ps/M05_AXI" ] }, - "S00_AXI4_3": { + "hier_ps_M32_AXI1": { "interface_ports": [ - "hier_gpio_2/S00_AXI4", - "hier_ps/M23_AXI" + "hier_ps/M32_AXI", + "hier_gpio_3/S00_AXI5" ] }, - "S00_AXI_1": { + "hier_ps_M35_AXI1": { "interface_ports": [ - "hier_powerstack/S00_AXI", - "hier_ps/M06_AXI" + "hier_ps/M35_AXI", + "hier_gpio_0/S00_AXI6" ] }, - "hier_ps_M34_AXI": { + "hier_ps_M34_AXI1": { "interface_ports": [ - "amdc_encoder_0/S00_AXI", - "hier_ps/M02_AXI" + "hier_ps/M34_AXI", + "hier_gpio_2/S00_AXI6" ] }, - "hier_ps_M31_AXI": { + "S00_AXI3_3": { "interface_ports": [ - "hier_ps/M31_AXI", - "hier_gpio_2/S00_AXI5" + "hier_gpio_2/S00_AXI3", + "hier_ps/M22_AXI" ] }, - "hier_ps_M33_AXI1": { + "S00_AXI4_3": { "interface_ports": [ - "amdc_timing_manager_0/S00_AXI", - "hier_ps/M33_AXI" + "hier_gpio_2/S00_AXI4", + "hier_ps/M23_AXI" ] }, - "processing_system7_0_DDR": { + "S00_AXI_3": { "interface_ports": [ - "DDR", - "hier_ps/DDR" + "hier_gpio_1/S00_AXI", + "hier_ps/M14_AXI" ] }, "S00_AXI4_4": { @@ -10162,22 +10344,22 @@ "hier_ps/M28_AXI" ] }, - "S00_AXI3_3": { + "S00_AXI1_1": { "interface_ports": [ - "hier_gpio_2/S00_AXI3", - "hier_ps/M22_AXI" + "hier_powerstack/S00_AXI1", + "hier_ps/M07_AXI" ] }, - "S00_AXI3_4": { + "S00_AXI2_1": { "interface_ports": [ - "hier_gpio_3/S00_AXI3", - "hier_ps/M27_AXI" + "hier_powerstack/S00_AXI2", + "hier_ps/M08_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI1_5": { "interface_ports": [ - "hier_gpio_0/S00_AXI3", - "hier_ps/M12_AXI" + "hier_gpio_3/S00_AXI1", + "hier_ps/M26_AXI" ] }, "hier_ps_M30_AXI": { @@ -10186,28 +10368,22 @@ "hier_gpio_1/S00_AXI5" ] }, - "S00_AXI3_2": { - "interface_ports": [ - "hier_gpio_1/S00_AXI3", - "hier_ps/M17_AXI" - ] - }, - "hier_ps_M36_AXI1": { + "S00_AXI_5": { "interface_ports": [ - "hier_ps/M36_AXI", - "hier_gpio_1/S00_AXI6" + "hier_gpio_3/S00_AXI", + "hier_ps/M24_AXI" ] }, - "hier_ps_M35_AXI1": { + "hier_ps_M29_AXI": { "interface_ports": [ - "hier_ps/M35_AXI", - "hier_gpio_0/S00_AXI6" + "hier_ps/M29_AXI", + "hier_gpio_0/S00_AXI5" ] }, - "S00_AXI1_1": { + "S00_AXI1_2": { "interface_ports": [ - "hier_powerstack/S00_AXI1", - "hier_ps/M07_AXI" + "hier_gpio_0/S00_AXI1", + "hier_ps/M11_AXI" ] }, "S00_AXI1_4": { @@ -10216,10 +10392,22 @@ "hier_ps/M21_AXI" ] }, - "S00_AXI1_3": { + "S00_AXI3_4": { "interface_ports": [ - "hier_gpio_1/S00_AXI1", - "hier_ps/M16_AXI" + "hier_gpio_3/S00_AXI3", + "hier_ps/M27_AXI" + ] + }, + "hier_ps_M34_AXI": { + "interface_ports": [ + "amdc_encoder_0/S00_AXI", + "hier_ps/M02_AXI" + ] + }, + "S00_AXI3_1": { + "interface_ports": [ + "hier_gpio_0/S00_AXI3", + "hier_ps/M12_AXI" ] }, "S00_AXI4_2": { @@ -10227,6 +10415,18 @@ "hier_gpio_1/S00_AXI4", "hier_ps/M18_AXI" ] + }, + "S00_AXI3_2": { + "interface_ports": [ + "hier_gpio_1/S00_AXI3", + "hier_ps/M17_AXI" + ] + }, + "S00_AXI4_1": { + "interface_ports": [ + "hier_gpio_0/S00_AXI4", + "hier_ps/M13_AXI" + ] } }, "nets": { @@ -10625,6 +10825,30 @@ "xlconcat_0/dout", "hier_ps/IRQ_F2P" ] + }, + "hier_ps_CAN0_tx": { + "ports": [ + "hier_ps/CAN0_TX", + "hier_gpio_3/CAN0_TX" + ] + }, + "hier_ps_CAN1_TX": { + "ports": [ + "hier_ps/CAN1_TX", + "hier_gpio_3/CAN1_TX" + ] + }, + "hier_gpio_3_CAN0_RX": { + "ports": [ + "hier_gpio_3/CAN0_RX", + "hier_ps/CAN0_RX" + ] + }, + "hier_gpio_3_CAN1_RX": { + "ports": [ + "hier_gpio_3/CAN1_RX", + "hier_ps/CAN1_RX" + ] } }, "comments": { diff --git a/sdk/app_cpu1/common/drv/can.c b/sdk/app_cpu1/common/drv/can.c index 3b3aee60..09fe0c1c 100644 --- a/sdk/app_cpu1/common/drv/can.c +++ b/sdk/app_cpu1/common/drv/can.c @@ -28,8 +28,10 @@ static XCanPs *CanPs; // Set the mode of the CAN device int can_setmode(can_mode_t mode) { + printf("gggg\n"); XCanPs *CanInstPtr = CanPs; uint32_t currMode = XCanPs_GetMode(CanInstPtr); + printf("ffff\n"); if (currMode == XCANPS_MODE_LOOPBACK && mode != CAN_CONFIG) { #ifdef CAN_DEBUG print("\nCAN peripheral currently in loopback mode. Can only enter config mode from here."); @@ -42,10 +44,11 @@ int can_setmode(can_mode_t mode) return FAILURE; } + printf("exit\n"); XCanPs_EnterMode(CanInstPtr, mode); - // Wait to reach specified mode, should happen instantaneously - while (XCanPs_GetMode(CanInstPtr) != mode) +// // Wait to reach specified mode, should happen instantaneously +// while (XCanPs_GetMode(CanInstPtr) != mode) ; return SUCCESS; } @@ -108,9 +111,6 @@ int can_set_peripheral(int device_id) int can_init(int device_id) { - // Set GPIO Device and Port - gp3io_mux_set_device(GP3IO_MUX_1_BASE_ADDR, GP3IO_MUX_DEVICE1); - XCanPs *CanInstPtr; u16 DeviceId; @@ -172,10 +172,17 @@ int can_init(int device_id) return FAILURE; } + printf("rrrr\n"); + // Enter Normal Mode to use CAN peripheral return can_setmode(XCANPS_MODE_NORMAL); } +int can_deinit() { + XCanPs_Reset(CanPs); + return SUCCESS; +} + // Send a CAN packet int can_send(uint8_t data[8], uint32_t num_bytes) { @@ -191,8 +198,8 @@ int can_send(uint8_t data[8], uint32_t num_bytes) packet.buffer[i] = data[i]; } - printf("\n%d\n", packet.message_id); - printf("%d\n", packet.num_bytes); + printf("\nID: %d\n", packet.message_id); + printf("Num Bytes:%d\n", packet.num_bytes); for (i = 0; i < 8; i++) { printf("%u ", packet.buffer[i]); } diff --git a/sdk/app_cpu1/common/drv/can.h b/sdk/app_cpu1/common/drv/can.h index 30d2ca77..39b67042 100644 --- a/sdk/app_cpu1/common/drv/can.h +++ b/sdk/app_cpu1/common/drv/can.h @@ -37,7 +37,7 @@ * Reference Manual, the actual value is one more than the value written to the register. * Thus, we write a value of 2 to the register, but the actual value is 3, which it should be. */ -#define DEFAULT_BAUD_PRESCALAR 2 +#define DEFAULT_BAUD_PRESCALAR 16 #define DEFAULT_CAN_MESSAGE_ID 1 // Different CAN modes @@ -64,6 +64,7 @@ int can_set_peripheral(int device_id); // Initialize the CAN peripheral int can_init(int device_id); +int can_deinit(); // Send and get CAN packets int can_send(uint8_t data[8], uint32_t num_bytes); diff --git a/sdk/app_cpu1/user/.cproject b/sdk/app_cpu1/user/.cproject index eb596242..407e89a3 100644 --- a/sdk/app_cpu1/user/.cproject +++ b/sdk/app_cpu1/user/.cproject @@ -25,8 +25,10 @@ + -