ZJIT: Replace non-ASCII chars in comments with ASCII equivalents (ruby#16975)

Author: tekknolagi

zjit/src/backend/arm64/mod.rs

@@ -685,7 +685,7 @@ impl Assembler {
                     // Convert MemBase::Stack to MemBase::Reg(NATIVE_BASE_PTR) with the
                     // correct stack displacement. The stack slot value lives directly at
                     // [NATIVE_BASE_PTR + stack_disp], so we just adjust the base and
-                    // combine displacements — no indirection needed. Large
+                    // combine displacements -- no indirection needed. Large
                     // displacements are handled by split_stack_membase().
                     let Mem { base, disp: stack_disp, .. } = stack_state.stack_membase_to_mem(stack_membase);
                     Opnd::Mem(Mem { base, disp: stack_disp + opnd_disp, num_bits: opnd_num_bits })

zjit/src/backend/lir.rs

@@ -2458,7 +2458,7 @@ impl Assembler
 
                     if survivors.is_empty() {
                         if call_result_live {
-                            // No survivors to restore — move result directly to output.
+                            // No survivors to restore -- move result directly to output.
                             let out = Self::rewritten_opnd(out, assignments);
                             new_insns.push(Insn::Mov { dest: out, src: C_RET_OPND });
                             new_ids.push(None);
@@ -3257,7 +3257,7 @@ impl fmt::Display for Assembler {
         }
 
         // Use sorted_blocks() instead of block_order() because block_order()
-        // calls rpo() → edges() which requires all blocks end with terminators.
+        // calls rpo() -> edges() which requires all blocks end with terminators.
         // After arm64_scratch_split, blocks may not have terminators.
         for bb in self.sorted_blocks() {
             let params = &bb.parameters;
@@ -4323,7 +4323,7 @@ mod tests {
         asm.number_instructions(16);
         let intervals = asm.build_intervals(live_in);
 
-        // 3 registers — only r10 needs to spill
+        // 3 registers -- only r10 needs to spill
         let preferred_registers = asm.preferred_register_assignments(&intervals);
         let (assignments, num_stack_slots) = asm.linear_scan(intervals, 3, &preferred_registers);
 
@@ -4351,7 +4351,7 @@ mod tests {
         asm.number_instructions(16);
         let intervals = asm.build_intervals(live_in);
 
-        // Only 1 register available — forces spills
+        // Only 1 register available -- forces spills
         let preferred_registers = asm.preferred_register_assignments(&intervals);
         let (assignments, num_stack_slots) = asm.linear_scan(intervals, 1, &preferred_registers);
 
@@ -4431,9 +4431,9 @@ mod tests {
         use crate::backend::current::ALLOC_REGS;
         let regs = &ALLOC_REGS[..5];
 
-        // Edge b1→b2 (single succ): args=[UImm(1), v1], params=[v2, v3]
-        // v1→Reg(1), v2→Reg(1), v3→Reg(2)
-        // Reg copy: Reg(1)→Reg(2) → Mov(regs[2], regs[1])
+        // Edge b1->b2 (single succ): args=[UImm(1), v1], params=[v2, v3]
+        // v1->Reg(1), v2->Reg(1), v3->Reg(2)
+        // Reg copy: Reg(1)->Reg(2) -> Mov(regs[2], regs[1])
         // Imm move: Mov(regs[1], UImm(1))
         // Inserted in b1 before Jmp: [Label, Mov, Mov, Jmp]
         let b1_insns = &asm.basic_blocks[b1.0].insns;
@@ -4443,10 +4443,10 @@ mod tests {
         assert!(matches!(&b1_insns[2], Insn::Mov { dest, src }
             if *dest == Opnd::Reg(regs[1]) && *src == Opnd::UImm(1)));
 
-        // Edge b3→b2 (single succ): args=[v4, v5], params=[v2, v3]
-        // v4→Reg(3), v5→Reg(2), v2→Reg(1), v3→Reg(2)
-        // Reg copy: Reg(3)→Reg(1) → Mov(regs[1], regs[3])
-        // Reg(2)→Reg(2) is self-move, filtered
+        // Edge b3->b2 (single succ): args=[v4, v5], params=[v2, v3]
+        // v4->Reg(3), v5->Reg(2), v2->Reg(1), v3->Reg(2)
+        // Reg copy: Reg(3)->Reg(1) -> Mov(regs[1], regs[3])
+        // Reg(2)->Reg(2) is self-move, filtered
         // Inserted in b3 before Jmp: [Label, Mul, Sub, Mov, Jmp]
         let b3_insns = &asm.basic_blocks[b3.0].insns;
         assert_eq!(b3_insns.len(), 5);
@@ -4455,7 +4455,7 @@ mod tests {
 
         // Verify original instructions in b3 are rewritten to physical registers.
         // b3: Mul { left: r12, right: r13, out: r14 }, Sub { left: r13, right: UImm(1), out: r15 }
-        // r12→Reg(1), r13→Reg(2), r14→Reg(3), r15→Reg(2)
+        // r12->Reg(1), r13->Reg(2), r14->Reg(3), r15->Reg(2)
         assert!(matches!(&b3_insns[1], Insn::Mul { left, right, out }
             if *left == Opnd::Reg(regs[1]) && *right == Opnd::Reg(regs[2]) && *out == Opnd::Reg(regs[3])));
         assert!(matches!(&b3_insns[2], Insn::Sub { left, right, out }
@@ -4473,16 +4473,16 @@ mod tests {
         let (assignments, _) = asm.linear_scan(intervals.clone(), 5, &preferred_registers);
 
         // Entry block b1 has parameters [v0, v1].
-        // With 5 registers: v0 → Reg(0) = regs[0], arrival = param_opnd(0) = regs[0] → self-move, filtered
-        //                    v1 → Reg(1) = regs[1], arrival = param_opnd(1) = regs[1] → self-move, filtered
+        // With 5 registers: v0 -> Reg(0) = regs[0], arrival = param_opnd(0) = regs[0] -> self-move, filtered
+        //                    v1 -> Reg(1) = regs[1], arrival = param_opnd(1) = regs[1] -> self-move, filtered
         // Before resolve_ssa, b1 has: [Label, Jmp] = 2 insns
         assert_eq!(asm.basic_blocks[b1.0].insns.len(), 2);
 
         asm.resolve_ssa(&intervals, &assignments);
 
         // After resolve_ssa, b1 should still have the same number of insns
         // (plus any edge moves, but no entry param moves since they're all self-moves).
-        // Edge b1→b2 inserts 2 moves before Jmp: [Label, Mov, Mov, Jmp] = 4 insns
+        // Edge b1->b2 inserts 2 moves before Jmp: [Label, Mov, Mov, Jmp] = 4 insns
         // No additional entry param moves.
         let b1_insns = &asm.basic_blocks[b1.0].insns;
         assert_eq!(b1_insns.len(), 4);
@@ -4508,8 +4508,8 @@ mod tests {
         let b3 = asm.new_block(hir::BlockId(2), false, 2);
 
         // b1: v0 = Add(123, 0), v1 = Add(v0, 456), Cmp(v1, 0), Jl(b2, [v0]), Jmp(b3, [v1])
-        // v0 is live across b1→b2 edge AND v1 is live across b1→b3 edge
-        // This forces v0 and v1 to have overlapping live ranges → different registers
+        // v0 is live across b1->b2 edge AND v1 is live across b1->b3 edge
+        // This forces v0 and v1 to have overlapping live ranges -> different registers
         asm.set_current_block(b1);
         let label_b1 = asm.new_label("bb0");
         asm.write_label(label_b1);
@@ -4562,8 +4562,8 @@ mod tests {
 
         asm.resolve_ssa(&intervals, &assignments);
 
-        // A new interstitial block should have been created for the critical edge b1→b3
-        // b1→b3 is critical because b1 has 2 successors and b3 has 2 predecessors
+        // A new interstitial block should have been created for the critical edge b1->b3
+        // b1->b3 is critical because b1 has 2 successors and b3 has 2 predecessors
         assert_eq!(asm.basic_blocks.len(), 4);
         let split_block_id = BlockId(3);
 
@@ -4587,11 +4587,11 @@ mod tests {
             panic!("Expected Jmp(b3) at end of split block");
         }
 
-        // The split block should have a Mov for v1→v4
+        // The split block should have a Mov for v1->v4
         let has_mov = split_insns.iter().any(|insn| matches!(insn, Insn::Mov { .. }));
-        assert!(has_mov, "Expected Mov in split block for v1→v4");
+        assert!(has_mov, "Expected Mov in split block for v1->v4");
 
-        // b2→b3 is not a critical edge (b2 has single succ), so moves go before Jmp in b2
+        // b2->b3 is not a critical edge (b2 has single succ), so moves go before Jmp in b2
         let v3_alloc = assignments[v3.vreg_idx().0].unwrap();
         let b2_insns = &asm.basic_blocks[b2.0].insns;
         if v3_alloc != v4_alloc {

zjit/src/backend/x86_64/mod.rs

@@ -112,7 +112,7 @@ const SCRATCH1_OPND: Opnd = Opnd::Reg(R10_REG);
 pub const SCRATCH_REG: Reg = R11_REG;
 
 impl Assembler {
-    // This keeps frame growth below the ±4096-byte displacement range we rely
+    // This keeps frame growth below the +/-4096-byte displacement range we rely
     // on for common stack-slot accesses on x86_64.
     const MAX_FRAME_STACK_SLOTS: usize = 2048;
 
@@ -142,7 +142,7 @@ impl Assembler {
     }
 
     // These are the callee-saved registers in the x86-64 SysV ABI
-    // RBX, RSP, RBP, and R12–R15
+    // RBX, RSP, RBP, and R12-R15
 
     /// Split IR instructions for the x86 platform
     fn x86_split(mut self) -> Assembler
@@ -357,7 +357,7 @@ impl Assembler {
                     // Convert MemBase::Stack to MemBase::Reg(NATIVE_BASE_PTR) with the
                     // correct stack displacement. The stack slot value lives directly at
                     // [NATIVE_BASE_PTR + stack_disp], so we just adjust the base and
-                    // combine displacements — no indirection needed.
+                    // combine displacements -- no indirection needed.
                     let Mem { base, disp: stack_disp, .. } = stack_state.stack_membase_to_mem(stack_membase);
                     Opnd::Mem(Mem { base, disp: stack_disp + opnd_disp, num_bits: opnd_num_bits })
                 }

zjit/src/codegen.rs

@@ -314,7 +314,7 @@ fn gen_iseq(cb: &mut CodeBlock, iseq: IseqPtr, function: Option<&Function>) -> R
     }
 
     // Compile the ISEQ. When function is None, this is a lazy compile
-    // from a stub hit — wrap in a trace event covering the full compile.
+    // from a stub hit -- wrap in a trace event covering the full compile.
     let mut version = IseqVersion::new(iseq);
     let code_ptrs = if function.is_none() {
         trace_compile_phase(&iseq_get_location(iseq, 0), || gen_iseq_body(cb, iseq, version, function))
@@ -387,15 +387,15 @@ fn gen_function(cb: &mut CodeBlock, iseq: IseqPtr, version: IseqVersionRef, func
 
         // Create all LIR basic blocks corresponding to HIR basic blocks
         for (rpo_idx, &block_id) in reverse_post_order.iter().enumerate() {
-            // Skip the entries superblock — it's an internal CFG artifact
+            // Skip the entries superblock -- it's an internal CFG artifact
             if block_id == function.entries_block { continue; }
             let lir_block_id = asm.new_block(block_id, function.is_entry_block(block_id), rpo_idx);
             hir_to_lir[block_id.0] = Some(lir_block_id);
         }
 
         // Compile each basic block
         for &block_id in reverse_post_order.iter() {
-            // Skip the entries superblock — it's an internal CFG artifact
+            // Skip the entries superblock -- it's an internal CFG artifact
             if block_id == function.entries_block { continue; }
             // Set the current block to the LIR block that corresponds to this
             // HIR block.
@@ -2069,22 +2069,22 @@ fn gen_is_a(jit: &mut JITState, asm: &mut Assembler, obj: Opnd, class: Opnd) ->
 
         let val = asm.load_mem(obj);
 
-        // Immediate → definitely not String/Array/Hash
+        // Immediate -> definitely not String/Array/Hash
         asm.test(val, Opnd::UImm(RUBY_IMMEDIATE_MASK as u64));
         asm.jnz(jit, result_edge(Qfalse.into()));
 
-        // Qfalse → definitely not String/Array/Hash
+        // Qfalse -> definitely not String/Array/Hash
         asm.cmp(val, Qfalse.into());
         asm.je(jit, result_edge(Qfalse.into()));
 
-        // Heap object → check builtin type
+        // Heap object -> check builtin type
         let flags = asm.load(Opnd::mem(VALUE_BITS, val, RUBY_OFFSET_RBASIC_FLAGS));
         let obj_builtin_type = asm.and(flags, Opnd::UImm(RUBY_T_MASK as u64));
         asm.cmp(obj_builtin_type, Opnd::UImm(builtin_type as u64));
         let result = asm.csel_e(Qtrue.into(), Qfalse.into());
         asm.jmp(result_edge(result));
 
-        // Result block — receives the value via block parameter (phi node)
+        // Result block -- receives the value via block parameter (phi node)
         asm.set_current_block(result_block);
         let label = jit.get_label(asm, result_block, hir_block_id);
         asm.write_label(label);
@@ -2458,21 +2458,21 @@ fn gen_has_type(jit: &mut JITState, asm: &mut Assembler, val: lir::Opnd, ty: Typ
         // TODO: Max thinks codegen should not care about the shapes of the operands except to create them. (Shopify/ruby#685)
         let val = asm.load_mem(val);
 
-        // Immediate → definitely not the class
+        // Immediate -> definitely not the class
         asm.test(val, (RUBY_IMMEDIATE_MASK as u64).into());
         asm.jnz(jit, result_edge(Opnd::Imm(0)));
 
-        // Qfalse → definitely not the class
+        // Qfalse -> definitely not the class
         asm.cmp(val, Qfalse.into());
         asm.je(jit, result_edge(Opnd::Imm(0)));
 
-        // Heap object → check klass field
+        // Heap object -> check klass field
         let klass = asm.load(Opnd::mem(64, val, RUBY_OFFSET_RBASIC_KLASS));
         asm.cmp(klass, Opnd::Value(expected_class));
         let result = asm.csel_e(Opnd::UImm(1), Opnd::Imm(0));
         asm.jmp(result_edge(result));
 
-        // Result block — receives the value via block parameter (phi node)
+        // Result block -- receives the value via block parameter (phi node)
         asm.set_current_block(result_block);
         let label = jit.get_label(asm, result_block, hir_block_id);
         asm.write_label(label);

zjit/src/hir.rs

@@ -6233,7 +6233,7 @@ impl<'a> std::fmt::Display for FunctionPrinter<'a> {
         writeln!(f, "fn {iseq_name}:")?;
         for block_id in fun.rpo() {
             if !self.display_snapshot_and_tp_patchpoints && block_id == fun.entries_block {
-                // Unless we're doing --zjit-dump-hir=all, skip the entries superblock — it's an
+                // Unless we're doing --zjit-dump-hir=all, skip the entries superblock -- it's an
                 // internal CFG artifact
                 continue;
             }
@@ -7041,7 +7041,7 @@ pub fn iseq_to_hir(iseq: *const rb_iseq_t) -> Result<Function, ParseError> {
                         // gen_is_block_given) to check for a block handler. Precompute the lexical
                         // distance from this iseq up to local_iseq so codegen does not have to
                         // walk the parent chain. Any DEFINED_YIELD reaching this branch has a
-                        // method local_iseq by construction — the above branch has already
+                        // method local_iseq by construction -- the above branch has already
                         // diverted the non-method case to Qnil.
                         let lep_level = if op_type == DEFINED_YIELD as usize {
                             get_lvar_level(iseq)
@@ -8606,7 +8606,7 @@ impl Dominators {
         let rpo = f.rpo();
         let num_blocks = f.blocks.len();
 
-        // Map BlockId → RPO index for O(1) lookup in intersect.
+        // Map BlockId -> RPO index for O(1) lookup in intersect.
         let mut rpo_order = vec![usize::MAX; num_blocks];
         for (idx, &block) in rpo.iter().enumerate() {
             rpo_order[block.0] = idx;

zjit/src/hir/opt_tests.rs

@@ -15683,7 +15683,7 @@ mod hir_opt_tests {
 
     #[test]
     fn test_recompile_no_profile_send() {
-        // Test the SideExit → recompile flow: a no-profile send becomes a SideExit,
+        // Test the SideExit -> recompile flow: a no-profile send becomes a SideExit,
         // the exit profiles the send, triggers recompilation, and the new version
         // optimizes it to SendDirect.
         eval("

zjit/src/virtualmem.rs

@@ -113,11 +113,11 @@ impl VirtualMem {
 
         // Memory protection syscalls need page-aligned addresses, so check it here. Assuming
         // `virt_block` is page-aligned, `second_half` should be page-aligned as long as the
-        // page size in bytes is a power of two 2¹⁹ or smaller. This is because the user
-        // requested size is half of mem_option × 2²⁰ as it's in MiB.
+        // page size in bytes is a power of two 2^19 or smaller. This is because the user
+        // requested size is half of mem_option * 2^20 as it's in MiB.
         //
         // Basically, we don't support x86-64 2MiB and 1GiB pages. ARMv8 can do up to 64KiB
-        // (2¹⁶ bytes) pages, which should be fine. 4KiB pages seem to be the most popular though.
+        // (2^16 bytes) pages, which should be fine. 4KiB pages seem to be the most popular though.
         let page_size = unsafe { rb_jit_get_page_size() };
         assert_eq!(
             virt_block as usize % page_size as usize, 0,