cache.vcd

$date
	Sun Jul 12 01:16:31 2026
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module tb_direct_mapped_cache $end
$var wire 1 ! mem_write $end
$var wire 32 " mem_wdata [31:0] $end
$var wire 1 # mem_req $end
$var wire 1 $ mem_ready $end
$var wire 32 % mem_rdata [31:0] $end
$var wire 32 & mem_addr [31:0] $end
$var wire 1 ' cpu_ready $end
$var wire 32 ( cpu_rdata [31:0] $end
$var parameter 32 ) ADDR_WIDTH $end
$var parameter 32 * BLOCKS $end
$var parameter 32 + DATA_WIDTH $end
$var parameter 32 , MEM_WORDS $end
$var reg 1 - clk $end
$var reg 32 . cpu_addr [31:0] $end
$var reg 1 / cpu_req $end
$var reg 32 0 cpu_wdata [31:0] $end
$var reg 1 1 cpu_write $end
$var reg 1 2 reset $end
$var integer 32 3 fail_count [31:0] $end
$var integer 32 4 pass_count [31:0] $end
$scope module DUT $end
$var wire 1 - clk $end
$var wire 32 5 cpu_addr [31:0] $end
$var wire 1 / cpu_req $end
$var wire 32 6 cpu_wdata [31:0] $end
$var wire 1 1 cpu_write $end
$var wire 1 2 reset $end
$var wire 1 ! mem_write $end
$var wire 32 7 mem_wdata [31:0] $end
$var wire 1 # mem_req $end
$var wire 1 $ mem_ready $end
$var wire 32 8 mem_rdata [31:0] $end
$var wire 32 9 mem_addr [31:0] $end
$var wire 1 ' cpu_ready $end
$var wire 32 : cpu_rdata [31:0] $end
$var wire 1 ; cache_write_en $end
$var wire 1 < cache_valid_in $end
$var wire 1 = cache_valid $end
$var wire 26 > cache_tag_in [25:0] $end
$var wire 26 ? cache_tag [25:0] $end
$var wire 4 @ cache_index [3:0] $end
$var wire 1 A cache_dirty_in $end
$var wire 1 B cache_dirty $end
$var wire 32 C cache_data_in [31:0] $end
$var wire 32 D cache_data [31:0] $end
$var parameter 32 E ADDR_WIDTH $end
$var parameter 32 F BLOCKS $end
$var parameter 32 G DATA_WIDTH $end
$var parameter 32 H INDEX_WIDTH $end
$var parameter 32 I OFFSET_WIDTH $end
$var parameter 34 J TAG_WIDTH $end
$scope module cache_controller_inst $end
$var wire 1 K cache_hit $end
$var wire 4 L cache_index [3:0] $end
$var wire 1 - clk $end
$var wire 32 M cpu_addr [31:0] $end
$var wire 1 / cpu_req $end
$var wire 32 N cpu_wdata [31:0] $end
$var wire 1 1 cpu_write $end
$var wire 1 2 reset $end
$var wire 26 O req_tag [25:0] $end
$var wire 4 P req_index [3:0] $end
$var wire 1 $ mem_ready $end
$var wire 32 Q mem_rdata [31:0] $end
$var wire 1 = cache_valid $end
$var wire 26 R cache_tag [25:0] $end
$var wire 1 B cache_dirty $end
$var wire 32 S cache_data [31:0] $end
$var parameter 32 T ADDR_WIDTH $end
$var parameter 3 U ALLOCATE $end
$var parameter 32 V BLOCKS $end
$var parameter 32 W DATA_WIDTH $end
$var parameter 3 X IDLE $end
$var parameter 32 Y INDEX_WIDTH $end
$var parameter 3 Z LOOKUP $end
$var parameter 32 [ OFFSET_WIDTH $end
$var parameter 34 \ TAG_WIDTH $end
$var parameter 3 ] UPDATE $end
$var parameter 3 ^ WRITE_BACK $end
$var reg 32 _ cache_data_in [31:0] $end
$var reg 1 A cache_dirty_in $end
$var reg 26 ` cache_tag_in [25:0] $end
$var reg 1 < cache_valid_in $end
$var reg 1 ; cache_write_en $end
$var reg 32 a cpu_rdata [31:0] $end
$var reg 1 ' cpu_ready $end
$var reg 32 b mem_addr [31:0] $end
$var reg 1 # mem_req $end
$var reg 32 c mem_wdata [31:0] $end
$var reg 1 ! mem_write $end
$var reg 32 d req_addr [31:0] $end
$var reg 32 e req_wdata [31:0] $end
$var reg 1 f req_write $end
$var reg 3 g state [2:0] $end
$upscope $end
$scope module cache_memory_inst $end
$var wire 1 - clk $end
$var wire 32 h data_in [31:0] $end
$var wire 32 i data_out [31:0] $end
$var wire 1 A dirty_in $end
$var wire 1 B dirty_out $end
$var wire 4 j index [3:0] $end
$var wire 1 2 reset $end
$var wire 26 k tag_in [25:0] $end
$var wire 26 l tag_out [25:0] $end
$var wire 1 < valid_in $end
$var wire 1 = valid_out $end
$var wire 1 ; write_en $end
$var parameter 32 m ADDR_WIDTH $end
$var parameter 32 n BLOCKS $end
$var parameter 32 o DATA_WIDTH $end
$var parameter 32 p INDEX_WIDTH $end
$var parameter 32 q OFFSET_WIDTH $end
$var parameter 34 r TAG_WIDTH $end
$var integer 32 s i [31:0] $end
$upscope $end
$upscope $end
$scope module MEMORY $end
$var wire 1 - clk $end
$var wire 32 t mem_addr [31:0] $end
$var wire 1 # mem_req $end
$var wire 32 u mem_wdata [31:0] $end
$var wire 1 ! mem_write $end
$var wire 1 2 reset $end
$var wire 8 v saved_word_addr [7:0] $end
$var parameter 32 w ADDR_WIDTH $end
$var parameter 32 x DATA_WIDTH $end
$var parameter 32 y LATENCY $end
$var parameter 32 z MEM_AWIDTH $end
$var parameter 32 { MEM_WORDS $end
$var parameter 32 | OFFSET_WIDTH $end
$var reg 1 } busy $end
$var reg 32 ~ mem_rdata [31:0] $end
$var reg 1 $ mem_ready $end
$var reg 32 !" saved_addr [31:0] $end
$var reg 32 "" saved_wdata [31:0] $end
$var reg 1 #" saved_write $end
$var integer 32 $" counter [31:0] $end
$var integer 32 %" i [31:0] $end
$upscope $end
$scope task cpu_read $end
$var reg 32 &" address [31:0] $end
$var reg 32 '" expected [31:0] $end
$upscope $end
$scope task cpu_write_task $end
$var reg 32 (" address [31:0] $end
$var reg 32 )" data [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 |
b100000000 {
b1000 z
b11 y
b100000 x
b100000 w
b11010 r
b10 q
b100 p
b100000 o
b10000 n
b100000 m
b10 ^
b100 ]
b11010 \
b10 [
b1 Z
b100 Y
b0 X
b100000 W
b10000 V
b11 U
b100000 T
b11010 J
b10 I
b100 H
b100000 G
b10000 F
b100000 E
b100000000 ,
b100000 +
b10000 *
b100000 )
$end
#0
$dumpvars
bx )"
bx ("
bx '"
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b100000000 %"
bx $"
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bx v
bx u
bx t
bx s
bx l
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bx j
bx i
bx h
bx g
xf
bx e
bx d
bx c
bx b
bx a
bx `
bx _
bx S
bx R
bx Q
bx P
bx O
b0 N
b0 M
bx L
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bx D
bx C
xB
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bx @
bx ?
bx >
x=
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bx 8
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$end
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b11011110101011011011111011101111 6
b11011110101011011011111011101111 N
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b11011110101011011011111011101111 _
b11011110101011011011111011101111 h
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b11001010111111101011101010111110 N
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b10000100 5
b10000100 M
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b10000100 d
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b10 l
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b11001010111111101011101010111110 C
b11001010111111101011101010111110 _
b11001010111111101011101010111110 h
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b11001010111111101011101010111110 '"
b10000100 &"
0-
#515000
0;
0'
1B
b11001010111111101011101010111110 D
b11001010111111101011101010111110 S
b11001010111111101011101010111110 i
1-
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1/
01
b0 0
b0 6
b0 N
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b110 4
b0 g
1'
b11001010111111101011101010111110 (
b11001010111111101011101010111110 :
b11001010111111101011101010111110 a
1-
#540000
0-
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1-
#550000
0-
#555000
1-
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0-