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jmartinez-silabsjmartinez-silabs
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Update Generated files (autogen/config) of all boards (#177)
* Update config files from slc regen results. Update utility script to remove unwanted files and clean output dir for a full regen * Update Autogen and Config files for si917 boards
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Lines changed: 4371 additions & 1101 deletions

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‎board-support/efr32/efr32mg24/BRD2601B/config/sl_btctrl_config.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,26 @@
135135
#ifndef SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE
136136
#define SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE (0)
137137
#endif
138+
139+
// <o SL_BT_CONTROLLER_ADAPTIVITY_MODE> Adaptive Frequency Hopping operation mode
140+
// <SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY=> Active AFH
141+
// <SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY=> Passive AFH
142+
// <i> Choose between active AFH and passive AFH
143+
// <i> Default: Active AFH
144+
// <d> SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY
145+
#ifndef SL_BT_CONTROLLER_ADAPTIVITY_MODE
146+
#define SL_BT_CONTROLLER_ADAPTIVITY_MODE (SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY)
147+
#endif
148+
149+
// <o SL_BT_CONTROLLER_PA_CONFIG> Power Amplifier (PA) Configuration
150+
// <SL_BT_BLUETOOTH_PA_AUTOMODE=> Automode PA configuration
151+
// <SL_BT_BLUETOOTH_HIGHEST_PA=> Highest available PA configuration
152+
// <SL_BT_BLUETOOTH_RAIL_UTIL_PA=> RAIL Utility component PA configuration
153+
// <i> Select the Power Amplifier configuration
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// <i> Default: RAIL Utility component PA configuration
155+
#ifndef SL_BT_CONTROLLER_PA_CONFIG
156+
#define SL_BT_CONTROLLER_PA_CONFIG SL_BT_BLUETOOTH_RAIL_UTIL_PA
157+
#endif
138158
// </h> Bluetooth Controller Configuration
139159

140160
// <<< end of configuration section >>>

‎board-support/efr32/efr32mg24/BRD2601B/config/sl_clock_manager_tree_config.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,13 @@
105105
#endif
106106

107107
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
108+
// <SL_CLOCK_MANAGER_PCLK_DIV_MIN=> MIN
108109
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
109110
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
110111
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
111-
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
112+
// <d> SL_CLOCK_MANAGER_PCLK_DIV_MIN
112113
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
113-
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
114+
#define SL_CLOCK_MANAGER_PCLK_DIVIDER SL_CLOCK_MANAGER_PCLK_DIV_MIN
114115
#endif
115116

116117
// </h>

‎board-support/efr32/efr32mg24/BRD2703A/config/sl_btctrl_config.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,26 @@
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#ifndef SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE
136136
#define SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE (0)
137137
#endif
138+
139+
// <o SL_BT_CONTROLLER_ADAPTIVITY_MODE> Adaptive Frequency Hopping operation mode
140+
// <SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY=> Active AFH
141+
// <SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY=> Passive AFH
142+
// <i> Choose between active AFH and passive AFH
143+
// <i> Default: Active AFH
144+
// <d> SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY
145+
#ifndef SL_BT_CONTROLLER_ADAPTIVITY_MODE
146+
#define SL_BT_CONTROLLER_ADAPTIVITY_MODE (SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY)
147+
#endif
148+
149+
// <o SL_BT_CONTROLLER_PA_CONFIG> Power Amplifier (PA) Configuration
150+
// <SL_BT_BLUETOOTH_PA_AUTOMODE=> Automode PA configuration
151+
// <SL_BT_BLUETOOTH_HIGHEST_PA=> Highest available PA configuration
152+
// <SL_BT_BLUETOOTH_RAIL_UTIL_PA=> RAIL Utility component PA configuration
153+
// <i> Select the Power Amplifier configuration
154+
// <i> Default: RAIL Utility component PA configuration
155+
#ifndef SL_BT_CONTROLLER_PA_CONFIG
156+
#define SL_BT_CONTROLLER_PA_CONFIG SL_BT_BLUETOOTH_RAIL_UTIL_PA
157+
#endif
138158
// </h> Bluetooth Controller Configuration
139159

140160
// <<< end of configuration section >>>

‎board-support/efr32/efr32mg24/BRD2703A/config/sl_clock_manager_tree_config.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,13 @@
105105
#endif
106106

107107
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
108+
// <SL_CLOCK_MANAGER_PCLK_DIV_MIN=> MIN
108109
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
109110
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
110111
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
111-
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
112+
// <d> SL_CLOCK_MANAGER_PCLK_DIV_MIN
112113
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
113-
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
114+
#define SL_CLOCK_MANAGER_PCLK_DIVIDER SL_CLOCK_MANAGER_PCLK_DIV_MIN
114115
#endif
115116

116117
// </h>

‎board-support/efr32/efr32mg24/BRD4186A/config/sl_btctrl_config.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,26 @@
135135
#ifndef SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE
136136
#define SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE (0)
137137
#endif
138+
139+
// <o SL_BT_CONTROLLER_ADAPTIVITY_MODE> Adaptive Frequency Hopping operation mode
140+
// <SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY=> Active AFH
141+
// <SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY=> Passive AFH
142+
// <i> Choose between active AFH and passive AFH
143+
// <i> Default: Active AFH
144+
// <d> SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY
145+
#ifndef SL_BT_CONTROLLER_ADAPTIVITY_MODE
146+
#define SL_BT_CONTROLLER_ADAPTIVITY_MODE (SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY)
147+
#endif
148+
149+
// <o SL_BT_CONTROLLER_PA_CONFIG> Power Amplifier (PA) Configuration
150+
// <SL_BT_BLUETOOTH_PA_AUTOMODE=> Automode PA configuration
151+
// <SL_BT_BLUETOOTH_HIGHEST_PA=> Highest available PA configuration
152+
// <SL_BT_BLUETOOTH_RAIL_UTIL_PA=> RAIL Utility component PA configuration
153+
// <i> Select the Power Amplifier configuration
154+
// <i> Default: RAIL Utility component PA configuration
155+
#ifndef SL_BT_CONTROLLER_PA_CONFIG
156+
#define SL_BT_CONTROLLER_PA_CONFIG SL_BT_BLUETOOTH_RAIL_UTIL_PA
157+
#endif
138158
// </h> Bluetooth Controller Configuration
139159

140160
// <<< end of configuration section >>>

‎board-support/efr32/efr32mg24/BRD4186A/config/sl_clock_manager_tree_config.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,13 @@
105105
#endif
106106

107107
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
108+
// <SL_CLOCK_MANAGER_PCLK_DIV_MIN=> MIN
108109
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
109110
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
110111
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
111-
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
112+
// <d> SL_CLOCK_MANAGER_PCLK_DIV_MIN
112113
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
113-
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
114+
#define SL_CLOCK_MANAGER_PCLK_DIVIDER SL_CLOCK_MANAGER_PCLK_DIV_MIN
114115
#endif
115116

116117
// </h>

‎board-support/efr32/efr32mg24/BRD4186C/config/sl_btctrl_config.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,26 @@
135135
#ifndef SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE
136136
#define SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE (0)
137137
#endif
138+
139+
// <o SL_BT_CONTROLLER_ADAPTIVITY_MODE> Adaptive Frequency Hopping operation mode
140+
// <SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY=> Active AFH
141+
// <SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY=> Passive AFH
142+
// <i> Choose between active AFH and passive AFH
143+
// <i> Default: Active AFH
144+
// <d> SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY
145+
#ifndef SL_BT_CONTROLLER_ADAPTIVITY_MODE
146+
#define SL_BT_CONTROLLER_ADAPTIVITY_MODE (SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY)
147+
#endif
148+
149+
// <o SL_BT_CONTROLLER_PA_CONFIG> Power Amplifier (PA) Configuration
150+
// <SL_BT_BLUETOOTH_PA_AUTOMODE=> Automode PA configuration
151+
// <SL_BT_BLUETOOTH_HIGHEST_PA=> Highest available PA configuration
152+
// <SL_BT_BLUETOOTH_RAIL_UTIL_PA=> RAIL Utility component PA configuration
153+
// <i> Select the Power Amplifier configuration
154+
// <i> Default: RAIL Utility component PA configuration
155+
#ifndef SL_BT_CONTROLLER_PA_CONFIG
156+
#define SL_BT_CONTROLLER_PA_CONFIG SL_BT_BLUETOOTH_RAIL_UTIL_PA
157+
#endif
138158
// </h> Bluetooth Controller Configuration
139159

140160
// <<< end of configuration section >>>

‎board-support/efr32/efr32mg24/BRD4186C/config/sl_clock_manager_tree_config.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,13 @@
105105
#endif
106106

107107
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
108+
// <SL_CLOCK_MANAGER_PCLK_DIV_MIN=> MIN
108109
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
109110
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
110111
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
111-
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
112+
// <d> SL_CLOCK_MANAGER_PCLK_DIV_MIN
112113
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
113-
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
114+
#define SL_CLOCK_MANAGER_PCLK_DIVIDER SL_CLOCK_MANAGER_PCLK_DIV_MIN
114115
#endif
115116

116117
// </h>

‎board-support/efr32/efr32mg24/BRD4187A/config/sl_btctrl_config.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,26 @@
135135
#ifndef SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE
136136
#define SL_BT_CONTROLLER_USE_LEGACY_VENDOR_SPECIFIC_EVENT_CODE (0)
137137
#endif
138+
139+
// <o SL_BT_CONTROLLER_ADAPTIVITY_MODE> Adaptive Frequency Hopping operation mode
140+
// <SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY=> Active AFH
141+
// <SL_BTCTRL_CHANNELMAP_FLAG_PASSIVE_ADAPTIVITY=> Passive AFH
142+
// <i> Choose between active AFH and passive AFH
143+
// <i> Default: Active AFH
144+
// <d> SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY
145+
#ifndef SL_BT_CONTROLLER_ADAPTIVITY_MODE
146+
#define SL_BT_CONTROLLER_ADAPTIVITY_MODE (SL_BTCTRL_CHANNELMAP_FLAG_ACTIVE_ADAPTIVITY)
147+
#endif
148+
149+
// <o SL_BT_CONTROLLER_PA_CONFIG> Power Amplifier (PA) Configuration
150+
// <SL_BT_BLUETOOTH_PA_AUTOMODE=> Automode PA configuration
151+
// <SL_BT_BLUETOOTH_HIGHEST_PA=> Highest available PA configuration
152+
// <SL_BT_BLUETOOTH_RAIL_UTIL_PA=> RAIL Utility component PA configuration
153+
// <i> Select the Power Amplifier configuration
154+
// <i> Default: RAIL Utility component PA configuration
155+
#ifndef SL_BT_CONTROLLER_PA_CONFIG
156+
#define SL_BT_CONTROLLER_PA_CONFIG SL_BT_BLUETOOTH_RAIL_UTIL_PA
157+
#endif
138158
// </h> Bluetooth Controller Configuration
139159

140160
// <<< end of configuration section >>>

‎board-support/efr32/efr32mg24/BRD4187A/config/sl_clock_manager_tree_config.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,12 +105,13 @@
105105
#endif
106106

107107
// <o SL_CLOCK_MANAGER_PCLK_DIVIDER> PCLK branch divider
108+
// <SL_CLOCK_MANAGER_PCLK_DIV_MIN=> MIN
108109
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV1=> DIV1
109110
// <CMU_SYSCLKCTRL_PCLKPRESC_DIV2=> DIV2
110111
// <i> PCLK branch is derived from HCLK. This clock drives the APB bus interface.
111-
// <d> CMU_SYSCLKCTRL_PCLKPRESC_DIV1
112+
// <d> SL_CLOCK_MANAGER_PCLK_DIV_MIN
112113
#ifndef SL_CLOCK_MANAGER_PCLK_DIVIDER
113-
#define SL_CLOCK_MANAGER_PCLK_DIVIDER CMU_SYSCLKCTRL_PCLKPRESC_DIV1
114+
#define SL_CLOCK_MANAGER_PCLK_DIVIDER SL_CLOCK_MANAGER_PCLK_DIV_MIN
114115
#endif
115116

116117
// </h>

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