C3 using bitsy software at 1k H/s not compiled HW SHA

[bwhiteman21-commits]

For any C3 trace shows HW SHA256 down to [init]all tasks created (single core mining)

Then says ====Sparkminer v2.8.0====
SHA-256 Implemenation: Software (Optimized)
Board: ESP-C3–SuperMini

[monitor] Task started on core 0
[miner0]started on core 0 (Bitsy Software SHA, …
…
[stats] Hashrate 1020 H/s …

Need to use S2/C3 fallback HAL based or as originally setup with DMA based compiled Hardware SHA256 and get more competitive to NerdMiner c3 of 350+ KH/s.

Feel updates to S2 asm upset this.

[SneezeGUI]

Diagnosed. The C3 wasn't regressed by the S2/S3 asm work — it was never wired to hardware SHA. Single-core SoCs only spawned the software miner task; the HAL hardware path was effectively dead code. And routing C3 to that old HAL task wouldn't have helped — it used the same unsupported SHA_H + SHA_CONTINUE midstate restore that breaks the S3 path (#28).

Fix → PR #39 (fix/c3-s2-hw-sha, draft): implements a correct hardware double-hash for C3/S2/S3 (sha256_ll_double_hash_full) using the legitimate START → CONTINUE flow with no midstate injection, routes single-core builds to it at low priority with frequent yields, and re-verifies every candidate in software before submitting (so a wrong HW hash can never become a bad share). The boot banner now honestly reports Hardware SHA.

It's a draft because it contains new register sequencing I couldn't test without a C3 in hand. If you build it with -D DEBUG_SHARE_VALIDATION, watch for [HW-DBG] ... SW verify=PASS and shares at the pool, well above the current ~1 KH/s.