fix(c3/s2): correct HW SHA full double-hash instead of software (#34)#39
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fix(c3/s2): correct HW SHA full double-hash instead of software (#34)#39SneezeGUI wants to merge 1 commit into
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This was referenced May 30, 2026
) ESP32-C3/S2 builds were mining in pure software (~1 KH/s) because setupTasks() spawned the software miner_task_core0 on single-core SoCs; the hardware HAL mining task (miner_task_core1) was never instantiated and was effectively dead code. The reporter's "Software (Optimized)" banner and low hashrate were the symptom. Simply routing C3 to the old HAL task would NOT have worked: its sha256_ll_double_hash() restores a midstate into SHA_H and issues SHA_CONTINUE, which the S2/S3/C3 SHA engine ignores (the same root cause as the S3 zero-shares bug, #28). So this: - Implements sha256_ll_double_hash_full() for S2/S3/C3 (previously a stub returning false). It hashes block 1 + block 2 with the legitimate START -> CONTINUE flow and the second SHA with a fresh START -- no external midstate injection -- which is correct on every variant. It re-hashes block 1 each nonce (no midstate cache), trading a little speed for correctness; still far faster than software. - Rewrites the C3/S2 miner_task_core1 to mine with that HW path and re-verify every candidate in software (miner_sha256_header) before submitting, so a wrong HW hash can never become a bad share. Enable -D DEBUG_SHARE_VALIDATION to log PASS/FAIL per candidate. - Routes single-core builds to miner_task_core1 at low priority with frequent yields, so WiFi/Stratum/Monitor stay responsive on the one core. - Fixes the boot banner: C3 envs now define USE_HARDWARE_SHA (was the dead USE_SOFTWARE_SHA), so the reported SHA implementation is honest. Needs on-device confirmation on an ESP32-C3 (watch for [HW-DBG] SW verify=PASS lines and shares landing at the pool). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Draft — contains new hardware register sequencing that has not been tested on a physical C3 yet.
Problem
ESP32-C3 mines in software at ~1 KH/s (#34). Cause: single-core SoCs only spawned the software miner task; the HAL HW path was dead code — and it used the same unsupported
SHA_H+SHA_CONTINUEmidstate restore as the S3 bug (#28), so routing C3 to it would also yield 0 shares.Fix
sha256_ll_double_hash_full()for S2/S3/C3 using the legitimateSTART → CONTINUEflow (no midstate injection), reusing this file's proven helpers.[HW-DBG]output, never a bad submission.-D DEBUG_SHARE_VALIDATION; confirm[HW-DBG] ... SW verify=PASSand shares at the pool, hashrate well above 1 KH/s.Closes #34.