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Bit of tidying
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megaavr/extras/Errata.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,8 @@ Errata apply to a specific die. But the same die may be used on multiple parts,
5151
* all 16k - This is clearly what was used for development - it's at rev E!
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* all 32k
5353

54-
## The grand combined table, now on google sheets
55-
[**The table is now in Google Sheets and publicly viewable - color coded too!**](https://docs.google.com/spreadsheets/d/1N-dDZ3WogEXRYcOip5kOREj_ExPQQRD1OrgMuywjXzw/edit?usp=sharing)
54+
## The grand combined table, now on Google Sheets
55+
[**The table is now in Google Sheets and publicly viewable - color coded too!**](https://docs.google.com/spreadsheets/d/1vRSt0s7Kpi_VehmFYBX8__OBbs7hbN87KwTNzwDcE2o/edit?usp=sharing)
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megaavr/libraries/SPI/README.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# SPI for megaTinyCore
2-
The SPI library implements all of the standard functionality described in the [Arduino SPI library reference](https://docs.arduino.cc/language-reference/en/functions/communication/spi/) - with the exception of the specific pins, of course!). Also, like all of the "big three" third-party cores for post-2016 AVR devices, this version of SPI.h supports the `swap()` and `pins()` methods to make use of the PORTMUX feature of the chips. Aside from those extensions, and a few changes to rarelty used, ill-conceived methods relating to interrupts, and unimplemented methods (likely intended for slave mode which was never implemented, for reasons discussed below), it behaves in the same way as the official one.
2+
The SPI library implements all of the standard functionality described in the [Arduino SPI library reference](https://docs.arduino.cc/language-reference/en/functions/communication/SPI/) applies here. With the exceptionific pins, of course!). Also, like all of the "big three" third-party cores for post-2016 AVR devices, this version of SPI.h supports the `swap()` and `pins()` methods to make use of the PORTMUX feature of the chips. Aside from those extensions, and a few changes to rarelty used, ill-conceived methods relating to interrupts, and unimplemented methods (likely intended for slave mode which was never implemented, for reasons discussed below), it behaves in the same way as the official one.
33

44
## Pins
55
| Pin Mapping | Pins | Parts | Note |

megaavr/tools/libs/intelhex/__init__.py

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ def _decode_record(self, s, line=0):
144144
if not self._buf.get(addr, None) is None:
145145
raise AddressOverlapError(address=addr, line=line)
146146
self._buf[addr] = bin[i]
147-
addr += 1 # FIXME: addr should be wrapped
147+
addr += 1 # FIXME: addr should be wrapped
148148
# BUT after 02 record (at 64K boundary)
149149
# and after 04 record (at 4G boundary)
150150

@@ -289,7 +289,7 @@ def frombytes(self, bytes, offset=0):
289289
def _get_start_end(self, start=None, end=None, size=None):
290290
"""Return default values for start and end if they are None.
291291
If this IntelHex object is empty then it's error to
292-
invoke this method with both start and end as None.
292+
invoke this method with both start and end as None.
293293
"""
294294
if (start,end) == (None,None) and self._buf == {}:
295295
raise EmptyIntelHexError
@@ -316,7 +316,7 @@ def _get_start_end(self, start=None, end=None, size=None):
316316
return start, end
317317

318318
def tobinarray(self, start=None, end=None, pad=_DEPRECATED, size=None):
319-
''' Convert this object to binary form as array. If start and end
319+
''' Convert this object to binary form as array. If start and end
320320
unspecified, they will be inferred from the data.
321321
@param start start address of output bytes.
322322
@param end end address of output bytes (inclusive).
@@ -419,7 +419,7 @@ def todict(self):
419419

420420
def addresses(self):
421421
'''Returns all used addresses in sorted order.
422-
@return list of occupied data addresses in sorted order.
422+
@return list of occupied data addresses in sorted order.
423423
'''
424424
aa = dict_keys(self._buf)
425425
aa.sort()
@@ -746,7 +746,7 @@ def puts(self, addr, s):
746746
self._buf[addr+i] = a[i]
747747

748748
def getsz(self, addr):
749-
"""Get zero-terminated bytes string from given address. Will raise
749+
"""Get zero-terminated bytes string from given address. Will raise
750750
NotEnoughDataError exception if a hole is encountered before a 0.
751751
"""
752752
i = 0
@@ -768,7 +768,7 @@ def putsz(self, addr, s):
768768
def find(self, sub, start=None, end=None):
769769
"""Return the lowest index in self[start:end] where subsection sub is found.
770770
Optional arguments start and end are interpreted as in slice notation.
771-
771+
772772
@param sub bytes-like subsection to find
773773
@param start start of section to search within (optional)
774774
@param end end of section to search within (optional)
@@ -798,7 +798,7 @@ def dump(self, tofile=None, width=16, withpadding=False):
798798
width = int(width)
799799
if tofile is None:
800800
tofile = sys.stdout
801-
801+
802802
# start addr possibly
803803
if self.start_addr is not None:
804804
cs = self.start_addr.get('CS')
@@ -853,7 +853,7 @@ def merge(self, other, overlap='error'):
853853
in overlapping region.
854854
855855
@raise TypeError if other is not instance of IntelHex
856-
@raise ValueError if other is the same object as self
856+
@raise ValueError if other is the same object as self
857857
(it can't merge itself)
858858
@raise ValueError if overlap argument has incorrect value
859859
@raise AddressOverlapError on overlapped data
@@ -908,7 +908,7 @@ def segments(self, min_gap=1):
908908
beginnings = [addresses[b+1] for b in breaks]
909909
beginnings.insert(0, addresses[0])
910910
return [(a, b+1) for (a, b) in zip(beginnings, endings)]
911-
911+
912912
def get_memory_size(self):
913913
"""Returns the approximate memory footprint for data."""
914914
n = sys.getsizeof(self)
@@ -996,7 +996,7 @@ def minaddr(self):
996996
def maxaddr(self):
997997
'''Get maximal address of HEX content in 16-bit mode.
998998
999-
@return maximal address used in this object
999+
@return maximal address used in this object
10001000
'''
10011001
aa = dict_keys(self._buf)
10021002
if aa == []:
@@ -1170,7 +1170,7 @@ def data(offset, bytes):
11701170

11711171
def eof():
11721172
"""Return End of File record as a string.
1173-
@return String representation of Intel Hex EOF record
1173+
@return String representation of Intel Hex EOF record
11741174
"""
11751175
return ':00000001FF'
11761176
eof = staticmethod(eof)
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
# IntelHex library version information
1+
# IntelHex library version information
22
version_info = (2, 3, 0)
33
version_str = '.'.join([str(i) for i in version_info])

megaavr/tools/libs/intelhex/test.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -765,7 +765,7 @@ def test__get_start_end(self):
765765
# normal object
766766
ih = IntelHex({1:2, 7:8, 10:0})
767767
self.assertEqual((1,10), ih._get_start_end())
768-
self.assertEqual((1,10), ih._get_start_end(size=10))
768+
self.assertEqual((1,10), ih._get_start_end(size=10))
769769
self.assertEqual((0,9), ih._get_start_end(start=0, size=10))
770770
self.assertEqual((1,10), ih._get_start_end(end=10, size=10))
771771

@@ -1092,7 +1092,7 @@ def test_simple_width3(self):
10921092
self.assertEqual(
10931093
'0000 12 34 -- |.4 |\n',
10941094
sio.getvalue())
1095-
1095+
10961096
ih[16] = 0x56
10971097
ih[30] = 0x98
10981098
sio = StringIO()
@@ -1682,7 +1682,7 @@ def runProcessAndGetAsciiStdoutOrStderr(self, cmdline):
16821682
if stdout:
16831683
output = stdout.decode('ascii', 'replace')
16841684
elif stderr:
1685-
output = stderr.decode('ascii', 'replace')
1685+
output = stderr.decode('ascii', 'replace')
16861686
output = output.replace('\r', '')
16871687
return retcode, output
16881688

@@ -1756,7 +1756,7 @@ def test_write_hex_file_byte_count_13(self):
17561756
s = sio.getvalue()
17571757
# control written hex first line to check that byte count is 13
17581758
sio.seek(0)
1759-
self.assertEqual(sio.readline(),
1759+
self.assertEqual(sio.readline(),
17601760
':0D0000000205A2E576246AF8E6057622786E\n',
17611761
"Written hex is not in byte count 13")
17621762
sio.close()
@@ -1774,7 +1774,7 @@ def test_write_hex_file_byte_count_255(self):
17741774
s = sio.getvalue()
17751775
# control written hex first line to check that byte count is 255
17761776
sio.seek(0)
1777-
self.assertEqual(sio.readline(),
1777+
self.assertEqual(sio.readline(),
17781778
(':FF0000000205A2E576246AF8E60576227867300702786AE475F0011204AD02'
17791779
'04552000EB7F2ED2008018EF540F2490D43440D4FF30040BEF24BFB41A0050'
17801780
'032461FFE57760021577057AE57A7002057930070D7867E475F0011204ADEF'

megaavr/tools/libs/pymcuprog/deviceinfo/harvest.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ def determine_write_size(memory_name, page_size, device_name):
6363
write_size = 1
6464
device_name = device_name.lower()
6565
if memory_name is 'flash':
66-
if (device_name.find('avr') != -1 and ((device_name.find('da') != -1) or (device_name.find('db') != -1) or (device_name.find('dd') != -1))):
66+
if (device_name.find('avr') != -1 and ((device_name.find('da') != -1) or (device_name.find('db') != -1) or (device_name.find('dd') != -1) or (device_name.find('du') != -1))):
6767
write_size = 2
6868
else:
6969
write_size = page_size

megaavr/tools/libs/pymcuprog/serialupdi/constants.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,8 @@
6262

6363
UPDI_KEY_NVM = b"NVMProg "
6464
UPDI_KEY_CHIPERASE = b"NVMErase"
65+
UPDI_KEY_UROWWRITE = b"NVMUs&te"
66+
UPDI_KEY_OCD = b"OCD "
6567

6668
UPDI_ASI_STATUSA_REVID = 4
6769
UPDI_ASI_STATUSB_PESIG = 0

megaavr/tools/libs/pymcuprog/serialupdi/link.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ def _check_datalink(self):
6969
self.logger.info("UPDI init OK")
7070
return True
7171
except PymcuprogError:
72-
self.logger.warning("UPDI init failed: Can't read CS register.")
72+
self.logger.warning("UPDI init failed: Can't read CS register. likely wiring error.")
7373
return False
7474
self.logger.info("UPDI not OK - reinitialisation required")
7575
return False

megaavr/tools/libs/pymcuprog/serialupdi/nvm.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -144,7 +144,7 @@ def write_fuse(self, address, data, write_delay=1):
144144

145145
# Check that NVM controller is ready
146146
if not self.wait_flash_ready():
147-
raise PymcuprogError("Timeout waiting for flash ready before page buffer clear ")
147+
raise PymcuprogError("Timeout waiting for flash ready before fuse write ")
148148

149149
# Write address to NVMCTRL ADDR
150150
self.logger.debug("Load NVM address")
@@ -162,7 +162,7 @@ def write_fuse(self, address, data, write_delay=1):
162162
if write_delay > 0:
163163
pause_mod.milliseconds(write_delay)
164164
if not self.wait_flash_ready():
165-
raise PymcuprogError("Timeout waiting for flash ready before page buffer clear ")
165+
raise PymcuprogError("Timeout waiting for flash ready after fuse write ")
166166

167167
def write_nvm(self, address, data, use_word_access, nvmcommand=constants.UPDI_V0_NVMCTRL_CTRLA_WRITE_PAGE, blocksize=2, bulkwrite=0, pagewrite_delay=0):
168168
"""
@@ -216,7 +216,7 @@ def write_nvm(self, address, data, use_word_access, nvmcommand=constants.UPDI_V0
216216
# do a final NVM status check only if not doing a bulk write, or after the last chunk (when bulkwrite = 2)
217217
# not doing this every page made uploads about 15% faster
218218
if not self.wait_flash_ready():
219-
raise PymcuprogError("Timeout waiting for flash ready after page write ")
219+
raise PymcuprogError("Timeout waiting for flash ready after write")
220220

221221

222222
class NvmUpdiAvrDx(NvmUpdi):
@@ -309,7 +309,7 @@ def write_nvm(self, address, data, use_word_access, blocksize=2, bulkwrite=0, pa
309309
if bulkwrite == 0 or (address & 32767) == 0:
310310
# Check that NVM controller is ready
311311
if not self.wait_flash_ready():
312-
raise Exception("Timeout waiting for flash ready before page buffer clear ")
312+
raise Exception("Timeout waiting for flash ready before nvm write ")
313313

314314
# Write the command to the NVM controller
315315
self.logger.info("NVM write command")

megaavr/tools/libs/yaml/constructor.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ def construct_mapping(self, node, deep=False):
123123
mapping = {}
124124
for key_node, value_node in node.value:
125125
key = self.construct_object(key_node, deep=deep)
126-
126+
127127
## Version Check
128128
python_version = sys.version
129129
version = python_version.split()[0]

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