USART0 RS-485 fails on ALT pins (USART1 OK) on ATtiny3227

[mechatroniks-git]

I think I've exhausted this issue and believe it's either a core issue or in the silicon.

TLDR:

ATtiny3227 + megaTinyCore: USART0 works on default pins, but USART0 dies on ALT1 specifically in RS-485/XDIR mode. USART1 works in all cases.

Your register dump shows everything is configured correctly (ALT1 mux, 115200 8N1, TX/RX enabled, RS-485 enabled) and USART0 believes it transmitted (TXCIF set), but the pins never drive. That points away from config and toward a deep USART0 ALT1 + RS-485/XDIR issue (MegaTinyCore bug or silicon errata).

---

Hardware

• MCU: ATtiny3227 (tested on 2 boards) @3.3V
• Core: megaTinyCore 2.6.12
• FQBN:megaTinyCore:megaavr:atxy7:clock=10internal,millis=timerb1,startuptime=64,printf=full
• Clock: internal 10 MHz
• Baud: 115200
• RS-485 transceivers with XDIR

Summary

RS-485 with hardware XDIR works correctly on both USART0 and USART1 when using default pin routing.

However, when moving both USARTs to ALT1 pins via PORTMUX.USARTROUTEA, USART1 continues to work correctly, but USART0 produces no output at all:
• No activity on TXD
• No activity on XDIR
• Internal USART0 state machine still completes transmissions (TXCIF asserts)

This was done to free the default USART0 XDIR pin due to an I²C SCL conflict.

Observed behavior

• Default routing:
  • USART0 RS-485: ✅ works
  • USART1 RS-485: ✅ works
• ALT1 routing (PORTMUX.USARTROUTEA = USART0_ALT1 | USART1_ALT1):
  • USART1 RS-232: ✅ works (TX correct)
  • USART0 RS-232: ✅ works (TX correct)
  • USART1 RS-485: ✅ works (TX + XDIR correct)
  • USART0 RS-485: ❌ no TXD output, ❌ no XDIR output
• Disabling RS-485 assist on USART0 (CTRLA = 0):
  • TX still does not appear on ALT1 TX pin
• USART0 internal behavior:
  • TXEN + RXEN enabled
  • BAUD, CTRLC correct
  • TXCIF sets after writes (verified by waiting on TXCIF and dumping registers)
  • Peripheral believes transmission completed, but pad is not driven
• GPIO sanity:
  • ALT1 TX/XDIR pins work correctly as GPIO
  • No probing or hardware issue (verified repeatedly)
  • USART1 ALT1 RS-485 works reliably with identical configuration.

I had ChatGPT write me a test program that would spit out the registers on the working port using as little of the core as possible

#include <avr/io.h>
#include <avr/interrupt.h>

static constexpr uint32_t UART_BAUD = 115200UL;

// tinyAVR 2-series fractional baud generator
static inline uint16_t baudReg(uint32_t baud) {
  return (uint16_t)((4UL * (uint32_t)F_CPU + baud / 2) / baud);
}

static inline void usart0_write(uint8_t c) {
  while (!(USART0.STATUS & USART_DREIF_bm)) {}
  USART0.TXDATAL = c;
}

static inline void usart1_write(uint8_t c) {
  while (!(USART1.STATUS & USART_DREIF_bm)) {}
  USART1.TXDATAL = c;
}

// -------------------- debug print helpers (USART1) --------------------

static void print_hex8(uint8_t v) {
  const char hex[] = "0123456789ABCDEF";
  usart1_write(hex[(v >> 4) & 0x0F]);
  usart1_write(hex[v & 0x0F]);
}

static void print_hex16(uint16_t v) {
  print_hex8((uint8_t)(v >> 8));
  print_hex8((uint8_t)(v & 0xFF));
}

static void print_str(const char *s) {
  while (*s) usart1_write(*s++);
}

static void nl(void) {
  usart1_write('\r');
  usart1_write('\n');
}

// -------------------- register dump --------------------

static void dump_regs(void) {
  print_str("=== REG DUMP ==="); nl();

  print_str("PORTMUX.USARTROUTEA = 0x"); print_hex8(PORTMUX.USARTROUTEA); nl();

  print_str("USART0.CTRLA  = 0x"); print_hex8(USART0.CTRLA); nl();
  print_str("USART0.CTRLB  = 0x"); print_hex8(USART0.CTRLB); nl();
  print_str("USART0.CTRLC  = 0x"); print_hex8(USART0.CTRLC); nl();
  print_str("USART0.BAUD   = 0x"); print_hex16(USART0.BAUD); nl();
  print_str("USART0.STATUS = 0x"); print_hex8(USART0.STATUS); nl();

  print_str("USART1.CTRLA  = 0x"); print_hex8(USART1.CTRLA); nl();
  print_str("USART1.CTRLB  = 0x"); print_hex8(USART1.CTRLB); nl();
  print_str("USART1.CTRLC  = 0x"); print_hex8(USART1.CTRLC); nl();
  print_str("USART1.BAUD   = 0x"); print_hex16(USART1.BAUD); nl();
  print_str("USART1.STATUS = 0x"); print_hex8(USART1.STATUS); nl();

  print_str("PORTA.DIR = 0x"); print_hex8(PORTA.DIR); nl();
  print_str("PORTA.OUT = 0x"); print_hex8(PORTA.OUT); nl();
  print_str("PORTA.IN  = 0x"); print_hex8(PORTA.IN); nl();

  print_str("PORTA.PIN1CTRL = 0x"); print_hex8(PORTA.PIN1CTRL); nl(); // PA1 TX0 ALT1
  print_str("PORTA.PIN2CTRL = 0x"); print_hex8(PORTA.PIN2CTRL); nl(); // PA2 RX0 ALT1
  print_str("PORTA.PIN3CTRL = 0x"); print_hex8(PORTA.PIN3CTRL); nl(); // PA3 XCK0 ALT1
  print_str("PORTA.PIN4CTRL = 0x"); print_hex8(PORTA.PIN4CTRL); nl(); // PA4 XDIR0 ALT1

  print_str("PORTC.DIR = 0x"); print_hex8(PORTC.DIR); nl();
  print_str("PORTC.OUT = 0x"); print_hex8(PORTC.OUT); nl();
  print_str("PORTC.IN  = 0x"); print_hex8(PORTC.IN); nl();

  print_str("PORTC.PIN0CTRL = 0x"); print_hex8(PORTC.PIN0CTRL); nl(); // PC0 XCK1 ALT1
  print_str("PORTC.PIN1CTRL = 0x"); print_hex8(PORTC.PIN1CTRL); nl(); // PC1 RX1 ALT1
  print_str("PORTC.PIN2CTRL = 0x"); print_hex8(PORTC.PIN2CTRL); nl(); // PC2 TX1 ALT1
  print_str("PORTC.PIN3CTRL = 0x"); print_hex8(PORTC.PIN3CTRL); nl(); // PC3 XDIR1 ALT1

  nl();
}

void setup() {
  cli();

  // Disable while configuring
  USART0.CTRLB = 0;
  USART1.CTRLB = 0;

  // Route both USARTs to ALT1 pins
  // USART0 ALT1: PA1(TX) PA2(RX) PA3(XCK) PA4(XDIR)
  // USART1 ALT1: PC2(TX) PC1(RX) PC0(XCK) PC3(XDIR)
  PORTMUX.USARTROUTEA = PORTMUX_USART0_ALT1_gc | PORTMUX_USART1_ALT1_gc;

  // Pin directions (TX + XDIR outputs, RX input)
  PORTA.DIRSET = PIN1_bm | PIN4_bm;
  PORTA.DIRCLR = PIN2_bm;
  PORTC.DIRSET = PIN2_bm | PIN3_bm;
  PORTC.DIRCLR = PIN1_bm;

  // Optional: your PA3 analog note (won't hurt here)
  PORTA.DIRCLR = PIN3_bm;
  PORTA.PIN3CTRL = PORT_ISC_INPUT_DISABLE_gc;

  // Idle receive (XDIR low)
  PORTA.OUTCLR = PIN4_bm;
  PORTC.OUTCLR = PIN3_bm;

  // Baud + 8N1 async
  const uint16_t br = baudReg(UART_BAUD);
  USART0.BAUD  = br;
  USART1.BAUD  = br;

  USART0.CTRLC = USART_CMODE_ASYNCHRONOUS_gc |
                 USART_PMODE_DISABLED_gc |
                 USART_CHSIZE_8BIT_gc;
  USART1.CTRLC = USART_CMODE_ASYNCHRONOUS_gc |
                 USART_PMODE_DISABLED_gc |
                 USART_CHSIZE_8BIT_gc;

  // RS-485 mode: hardware drives XDIR
  USART0.CTRLA = USART_RS485_bm;
  USART1.CTRLA = USART_RS485_bm;

  // Enable RX + TX
  USART0.CTRLB = USART_RXEN_bm | USART_TXEN_bm;
  USART1.CTRLB = USART_RXEN_bm | USART_TXEN_bm;

  sei();

  // One startup marker on USART1 so you know the console is alive
  print_str("BOOT"); nl();
}

void loop() {
  // Make USART0 TX unmistakable: a burst of 0x55 (01010101) is scope-friendly
  for (uint8_t i = 0; i < 64; i++) usart0_write(0x55);

  dump_regs();            // still prints over USART1
  usart1_write('B');      // optional marker

  for (volatile uint32_t i = 0; i < 300000; i++) {
    __asm__ __volatile__("nop");
  }
}

I get this dump

[00:37:03.253] [UART0] B
[00:37:04.240] [UART0] === REG DUMP ===\r\n
[00:37:04.243] [UART0] PORTMUX.USARTROUTEA = 0x05\r\n
[00:37:04.245] [UART0] USART0.CTRLA  = 0x01\r\n
[00:37:04.247] [UART0] USART0.CTRLB  = 0xC0\r\n
[00:37:04.249] [UART0] USART0.CTRLC  = 0x03\r\n
[00:37:04.251] [UART0] USART0.BAUD   = 0x015B\r\n
[00:37:04.253] [UART0] USART0.STATUS = 0x60\r\n
[00:37:04.254] [UART0] USART1.CTRLA  = 0x01\r\n
[00:37:04.256] [UART0] USART1.CTRLB  = 0xC0\r\n
[00:37:04.258] [UART0] USART1.CTRLC  = 0x03\r\n
[00:37:04.260] [UART0] USART1.BAUD   = 0x015B\r\n
[00:37:04.262] [UART0] USART1.STATUS = 0x40\r\n
[00:37:04.264] [UART0] PORTA.DIR = 0x12\r\n
[00:37:04.265] [UART0] PORTA.OUT = 0x00\r\n
[00:37:04.267] [UART0] PORTA.IN  = 0x8D\r\n
[00:37:04.269] [UART0] PORTA.PIN1CTRL = 0x00\r\n
[00:37:04.271] [UART0] PORTA.PIN2CTRL = 0x00\r\n
[00:37:04.273] [UART0] PORTA.PIN3CTRL = 0x04\r\n
[00:37:04.275] [UART0] PORTA.PIN4CTRL = 0x00\r\n
[00:37:04.276] [UART0] PORTC.DIR = 0x0C\r\n
[00:37:04.278] [UART0] PORTC.OUT = 0x08\r\n
[00:37:04.280] [UART0] PORTC.IN  = 0x1A\r\n
[00:37:04.282] [UART0] PORTC.PIN0CTRL = 0x00\r\n
[00:37:04.284] [UART0] PORTC.PIN1CTRL = 0x00\r\n
[00:37:04.285] [UART0] PORTC.PIN2CTRL = 0x00\r\n
[00:37:04.287] [UART0] PORTC.PIN3CTRL = 0x00\r\n
[00:37:04.288] [UART0] \r\n

Which confirms:

• Both USARTs are configured correctly and identically for 115200 8N1 with RX+TX enabled (CTRLB=0xC0, CTRLC=0x03, BAUD=0x015B).
• Both are routed to ALT1 pins (PORTMUX.USARTROUTEA=0x05 → USART0 ALT1 + USART1 ALT1).
• RS-485 mode is enabled on both (CTRLA=0x01).
• USART0 is idle/ready and thinks TX is complete (STATUS=0x60 = DREIF+TXCIF set) — i.e., the peripheral isn’t stuck.
• Pin directions match expectations (PORTA.DIR=0x12 → PA1/PA4 outputs; PORTC.DIR=0x0C → PC2/PC3 outputs).
• Nothing in the registers explains “no output”; it points to a pad/routing/driver issue specific to USART0 ALT1, not a configuration/baud/enable problem.

I'm about to give up on this chip. Anyone have any ideas for me?

[mechatroniks-git]

Heads up for anyone working with ATtiny3227 or related ATtiny 2-Series devices (82x, 162x, 32x series).

Microchip confirmed a silicon-level bug affecting USART0 when using ALT pin routing.

Here's what you need to know:

What's broken:

• USART0 does not correctly assert the RS-485 XDIR signal on the ALT pin location (PA4). This isn't just an RS-485 problem — all CMODEs are affected when ALT routing is selected for USART0.

What's not the problem:

• Default pin routing and ALT for USART1 both work fine.

Current status:

• The bug is documented internally and will appear in an upcoming official erratum for these devices.