Merge pull request #5 from project-inochi/upstream-1

buildroot: Add initial upstreamd buildroot support (sim with hypervisor)

Author: Dolu1990

buildroot/Config.in

@@ -1,2 +1 @@
-source "$BR2_EXTERNAL_NAXRISCV_SIM_PATH/package/opensbi-ext/Config.in"
 

buildroot/README.md

@@ -4,9 +4,8 @@
 ```
 cd $NAXRISCV/..
 export NAX_SOFTWARE=$NAXRISCV/ext/NaxSoftware
-git clone https://github.com/buildroot/buildroot.git --branch master
+git clone https://github.com/buildroot/buildroot.git --branch 2026.02.x
 cd buildroot
-git checkout 9ef54b7d
 $NAX_SOFTWARE/buildroot/naxriscv_sim_setup.sh rv32ima
 make BR2_EXTERNAL=$NAX_SOFTWARE/buildroot/ naxriscv_sim_defconfig
 make
@@ -15,10 +14,11 @@ make
 ## Opensbi
 
 ```
-git clone https://github.com/riscv-software-src/opensbi.git --branch  v0.8
+git clone https://github.com/riscv-software-src/opensbi.git --branch v1.8.1
 cd opensbi
+git am $NAX_SOFTWARE/buildroot/opensbi/0001-spinal-sim-related-device.patch
 export CROSS_COMPILE=riscv64-unknown-elf-
-make PLATFORM_RISCV_XLEN=64 PLATFORM_RISCV_ABI=lp64d PLATFORM_RISCV_ISA=rv64gc PLATFORM=out-of-tree
+make PLATFORM_RISCV_XLEN=64 PLATFORM_RISCV_ABI=lp64d BUILD_INFO=y DEBUG=1 FW_PIC=y PLATFORM=generic FW_TEXT_START=0x80000000 FW_JUMP_ADDR=0x80400000 FW_JUMP_FDT_ADDR=0x80F80000
 ```
 
 ## How to run sim
@@ -33,4 +33,4 @@ Follow the readme to build the simulator, then
 --load-bin $LINUX_IMAGES/rootfs.cpio,0x81000000 
 ```
 
-<3
+<3

buildroot/boards/naxriscv_sim/linux/linux_raw.config

@@ -2,6 +2,7 @@ CONFIG_SECTION_MISMATCH_WARN_ONLY=y
 
 ## Architecture
 CONFIG_ARCH_DEFCONFIG="arch/riscv/configs/defconfig"
+CONFIG_NONPORTABLE=y
 #ifdef RV32
 CONFIG_ARCH_RV32I=y
 #endif
@@ -17,6 +18,10 @@ CONFIG_FPU=y
 #else
 CONFIG_FPU=n
 #endif
+#ifdef RVH
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+#endif
 CONFIG_SMP=y
 CONFIG_STRICT_KERNEL_RWX=n
 CONFIG_EFI=n

buildroot/boards/naxriscv_sim/linux/linux_raw.dts

@@ -3,43 +3,62 @@
 ##include <dt-bindings/input/input.h>
 ##include <dt-bindings/interrupt-controller/irq.h>
 
+/ {
+	compatible = "spinal,vexiiriscv";
+	##address-cells = <1>;
+	##size-cells = <1>;
 
+	chosen {
+		bootargs = "rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init";
+		linux,initrd-start = <0x81000000>;
+		linux,initrd-end =   <0x81800000>;
+	};
 
-/ {
-    ##address-cells = <0x1>;
-    ##size-cells = <0x1>;
-    compatible = "spinal,naxriscv";
-    model = "spinal,naxriscv_sim";
-
-    chosen {
-        bootargs = "rootwait console=hvc0 earlycon=sbi root=/dev/ram0 init=/sbin/init";
-        linux,initrd-start = <0x81000000>;
-        linux,initrd-end =   <0x81800000>;
-    };
-
-    cpus {
-        ##address-cells = <0x1>;
-        ##size-cells = <0x0>;
-        timebase-frequency = <100000000>;
-        cpu@0 {
-            device_type = "cpu";
-            compatible = "riscv";
-            riscv,isa = ISA_STR;
-            mmu-type = MMU_TYPE;
-            reg = <0>;
-            status = "okay";
-            L0: interrupt-controller {
-                ##interrupt-cells = <0x00000001>;
-                interrupt-controller;
-                compatible = "riscv,cpu-intc";
-            };
-        };
-    };
-
-    memory@80000000 {
-        device_type = "memory";
-        reg = <0x80400000 0x0FC00000>;
-    };
-};
+	cpus {
+		##address-cells = <1>;
+		##size-cells = <0>;
+		timebase-frequency = <100000000>;
+
+		cpu@0 {
+			compatible = "spinal,vexiiriscv", "riscv";
+			reg = <0>;
+			device_type = "cpu";
+			mmu-type = MMU_TYPE;
+			riscv,isa-base = ISA_BASE;
+			riscv,isa-extensions = ISA_STR;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				##interrupt-cells = <1>;
+			};
+		};
+	};
 
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
 
+	soc {
+		compatible = "simple-bus";
+		##address-cells = <1>;
+		##size-cells = <1>;
+		ranges;
+
+		serial0: serial@10000000 {
+			compatible = "spinal,vexiiriscv-uart";
+			reg = <0x10000000 0x1000>;
+		};
+
+		clint: timer@10010000 {
+			compatible = "sifive,clint0";
+			reg = <0x10010000 0x10000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+	};
+
+	poweroff {
+		compatible = "spinal-poweroff";
+	};
+};