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source/SpinalHDL/Libraries/logic.rst

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@@ -3,27 +3,41 @@ Logic Simplification Utilities
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A minimal Boolean simplification and decode-table utility for decoders using quine-mcklusky.
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Provides masked pattern matching, Quine McCluskey style logic reduction, and a high-level decode-table builder.
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--- # Masked
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Represents a bit pattern with care (significant) and don t-care bits. `value` = bit values `care` = which bits must match (1 = match, 0 = don t care)
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**Main API:** * `covers(that)` check if one pattern includes another * `intersects(that)` check if patterns overlap * `mergeOneBitDifSmaller` merge patterns differing by one bit * `=== (bits)` hardware match under mask * `toString(bitCount)` shows bits with - for don t-care
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Represents a bit pattern with care (significant) and don't-care bits.
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`value` = bit values
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`care` = which bits must match (1 = match, 0 = don't care)
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**Main API:**
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* `covers(that)` check if one pattern includes another
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* `intersects(that)` check if patterns overlap
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* `mergeOneBitDifSmaller` merge patterns differing by one bit
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* `=== (bits)` hardware match under mask
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* `toString(bitCount)` shows bits with - for don't-care
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**Example:**
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.. code-block:: scala
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Masked(BigInt("0010", 2), BigInt("1111", 2))
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Masked(BigInt("0010", 2), Masked("1111", 2)), Masked(1--0)
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Used to define instruction encodings for decode tables.
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--- # Symplify Performs Boolean logic minimization for decode circuits.
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**Main API:** * `apply(input, mapping, resultWidth)` simplified decode logic * `apply(input, trueTerms)` simplified Boolean output * `trueAndDontCare(...)` simplified Boolean with explicit don t-care terms Based on Quine McCluskey; runs at elaboration time.
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**Main API:**
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* `apply(input, mapping, resultWidth)` simplified decode logic
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* `apply(input, trueTerms)` simplified Boolean output
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* `trueAndDontCare(...)` simplified Boolean with explicit don-t-care terms Based on Quine McCluskey; runs at elaboration time.
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--- # DecodingSpec High-level builder for decode tables using `Masked` patterns.
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**API:** * `setDefault(value)`
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* `addNeeds(key, value)`
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* `addNeeds(keys, value)`
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* `build(sel, coverAll)`
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generate simplified decode logic **Example:**
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generate simplified decode logic
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**Example:**
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.. code-block:: scala ```
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val spec = new DecodingSpec(UInt(4 bits))
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spec.setDefault(Masked(U"0011"))
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spec.addNeeds(Masked(B"000"), Masked(U"1000"))
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result := spec.build(sel, allPatterns)
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Generates minimized combinational decode logic.
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--- # Practical Use Define instruction patterns as `Masked` and feed them into `DecodingSpec` or `Symplify` to build compact decode logic for CPU instruction sets (e.g., RISC-V).
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--- # Notes * Simplification is cached and fast for large decode tables * Output hardware is minimized (fewer LUTs / simpler gates)
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--- # Practical Use
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Define bit patterns as `Masked` and feed them into `DecodingSpec` or `Symplify` to build compact decode logic for CPU instruction sets (e.g., RISC-V).
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* Output hardware is minimized (fewer LUTs / simpler gates)

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