update .pot files

Author: actions-user

source/locale/gettext/SpinalHDL/Simulation/clock.pot

@@ -8,7 +8,7 @@ msgid ""
 msgstr ""
 "Project-Id-Version: SpinalHDL \n"
 "Report-Msgid-Bugs-To: \n"
-"POT-Creation-Date: 2026-01-04 11:00+0000\n"
+"POT-Creation-Date: 2026-04-18 09:57+0000\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -33,8 +33,8 @@ msgid "ClockDomain stimulus functions"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:14
-#: ../../SpinalHDL/Simulation/clock.rst:48
-#: ../../SpinalHDL/Simulation/clock.rst:88
+#: ../../SpinalHDL/Simulation/clock.rst:57
+#: ../../SpinalHDL/Simulation/clock.rst:97
 msgid "Description"
 msgstr ""
 
@@ -43,272 +43,288 @@ msgid "``forkStimulus(period)``"
 msgstr ""
 
 #: ../../SpinalHDL/Simulation/clock.rst:16
-msgid "Fork a simulation process to generate the ClockDomain stimulus (clock, reset, softReset, clockEnable signals)"
+msgid "Fork a simulation process to generate the ClockDomain stimulus (clock, reset, softReset, clockEnable signals). The reset duration is 16 clock periods. The ``period`` is given as a number of simulation time units. An odd ``period`` will be truncated by one to have a symmetrical clock."
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:20
+msgid "``forkStimulus(period, sleepDuration [, resetCycles])``"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:21
+msgid "Similar to ``forkStimulus(period)`` but wait ``sleepDuration`` clock cycles after the reset is done and allows to specify ``resetCycles`` (default 16 cycles)"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:23
+msgid "``forkStimulus()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:17
+#: ../../SpinalHDL/Simulation/clock.rst:24
+msgid "Similar to ``forkStimulus(period)`` but the period is computed from the ``frequency`` field of the clock domain"
+msgstr ""
+
+#: ../../SpinalHDL/Simulation/clock.rst:26
 msgid "``forkSimSpeedPrinter(printPeriod)``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:18
+#: ../../SpinalHDL/Simulation/clock.rst:27
 msgid "Fork a simulation process which will periodically print the simulation speed in kilo-cycles per real time second. ``printPeriod`` is in realtime seconds"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:19
+#: ../../SpinalHDL/Simulation/clock.rst:28
 msgid "``clockToggle()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:20
+#: ../../SpinalHDL/Simulation/clock.rst:29
 msgid "Toggle the clock signal"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:21
+#: ../../SpinalHDL/Simulation/clock.rst:30
 msgid "``fallingEdge()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:22
+#: ../../SpinalHDL/Simulation/clock.rst:31
 msgid "Clear the clock signal"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:23
+#: ../../SpinalHDL/Simulation/clock.rst:32
 msgid "``risingEdge()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:24
+#: ../../SpinalHDL/Simulation/clock.rst:33
 msgid "Set the clock signal"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:25
+#: ../../SpinalHDL/Simulation/clock.rst:34
 msgid "``assertReset()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:26
+#: ../../SpinalHDL/Simulation/clock.rst:35
 msgid "Set the reset signal to its active level"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:27
+#: ../../SpinalHDL/Simulation/clock.rst:36
 msgid "``deassertReset()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:28
+#: ../../SpinalHDL/Simulation/clock.rst:37
 msgid "Set the reset signal to its inactive level"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:29
+#: ../../SpinalHDL/Simulation/clock.rst:38
 msgid "``assertClockEnable()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:30
-#: ../../SpinalHDL/Simulation/clock.rst:32
+#: ../../SpinalHDL/Simulation/clock.rst:39
+#: ../../SpinalHDL/Simulation/clock.rst:41
 msgid "Set the clockEnable signal to its active level"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:31
+#: ../../SpinalHDL/Simulation/clock.rst:40
 msgid "``deassertClockEnable()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:33
+#: ../../SpinalHDL/Simulation/clock.rst:42
 msgid "``assertSoftReset()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:34
-#: ../../SpinalHDL/Simulation/clock.rst:36
+#: ../../SpinalHDL/Simulation/clock.rst:43
+#: ../../SpinalHDL/Simulation/clock.rst:45
 msgid "Set the softReset signal to its active level"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:35
+#: ../../SpinalHDL/Simulation/clock.rst:44
 msgid "``deassertSoftReset()``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:39
+#: ../../SpinalHDL/Simulation/clock.rst:48
 msgid "Wait API"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:41
-#: ../../SpinalHDL/Simulation/clock.rst:81
+#: ../../SpinalHDL/Simulation/clock.rst:50
+#: ../../SpinalHDL/Simulation/clock.rst:90
 msgid "Below is a list of ``ClockDomain`` utilities that you can use to wait for a given event from the domain:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:47
+#: ../../SpinalHDL/Simulation/clock.rst:56
 msgid "ClockDomain wait functions"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:49
+#: ../../SpinalHDL/Simulation/clock.rst:58
 msgid "``waitSampling([cyclesCount])``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:50
+#: ../../SpinalHDL/Simulation/clock.rst:59
 msgid "Wait until the ``ClockDomain`` makes a sampling, (active clock edge && deassertReset && assertClockEnable)"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:51
+#: ../../SpinalHDL/Simulation/clock.rst:60
 msgid "``waitRisingEdge([cyclesCount])``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:52
+#: ../../SpinalHDL/Simulation/clock.rst:61
 msgid "Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 cycle if not otherwise specified. Note, cyclesCount = 0 is legal, and the function is not sensitive to reset/softReset/clockEnable"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:53
+#: ../../SpinalHDL/Simulation/clock.rst:62
 msgid "``waitFallingEdge([cyclesCount])``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:54
+#: ../../SpinalHDL/Simulation/clock.rst:63
 msgid "Same as ``waitRisingEdge`` but for the falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:55
+#: ../../SpinalHDL/Simulation/clock.rst:64
 msgid "``waitActiveEdge([cyclesCount])``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:56
+#: ../../SpinalHDL/Simulation/clock.rst:65
 msgid "Same as ``waitRisingEdge`` but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:57
+#: ../../SpinalHDL/Simulation/clock.rst:66
 msgid "``waitInactiveEdge([cyclesCount])``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:58
+#: ../../SpinalHDL/Simulation/clock.rst:67
 msgid "Same as ``waitFallingEdge`` but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:59
+#: ../../SpinalHDL/Simulation/clock.rst:68
 msgid "``waitRisingEdgeWhere(condition)``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:60
+#: ../../SpinalHDL/Simulation/clock.rst:69
 msgid "Same as ``waitRisingEdge``, but to exit, the boolean ``condition`` must be true when the rising edge occurs"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:61
+#: ../../SpinalHDL/Simulation/clock.rst:70
 msgid "``waitFallingEdgeWhere(condition)``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:62
+#: ../../SpinalHDL/Simulation/clock.rst:71
 msgid "Same as ``waitRisingEdgeWhere``, but for the falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:63
+#: ../../SpinalHDL/Simulation/clock.rst:72
 msgid "``waitActiveEdgeWhere(condition)``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:64
+#: ../../SpinalHDL/Simulation/clock.rst:73
 msgid "Same as ``waitRisingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:65
+#: ../../SpinalHDL/Simulation/clock.rst:74
 msgid "``waitInactiveEdgeWhere(condition)``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:66
+#: ../../SpinalHDL/Simulation/clock.rst:75
 msgid "Same as ``waitFallingEdgeWhere``, but for the edge level specified by the ``ClockDomainConfig``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:67
+#: ../../SpinalHDL/Simulation/clock.rst:76
 msgid "``waitSamplingWhere(condition) : Boolean``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:68
+#: ../../SpinalHDL/Simulation/clock.rst:77
 msgid "Wait until a clockdomain sampled and the given condition is true"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:69
+#: ../../SpinalHDL/Simulation/clock.rst:78
 msgid "``waitSamplingWhere(timeout)(condition) : Boolean``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:70
+#: ../../SpinalHDL/Simulation/clock.rst:79
 msgid "Same as waitSamplingWhere defined above, but will never block more than timeout cycles. Return true if the exit condition came from the timeout"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:74
+#: ../../SpinalHDL/Simulation/clock.rst:83
 msgid "All the functionality of the wait API can only be called directly from inside a thread, and not from a callback executed via the Callback API."
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:79
+#: ../../SpinalHDL/Simulation/clock.rst:88
 msgid "Callback API"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:87
+#: ../../SpinalHDL/Simulation/clock.rst:96
 msgid "ClockDomain callback functions"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:89
+#: ../../SpinalHDL/Simulation/clock.rst:98
 msgid "``onNextSampling { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:90
+#: ../../SpinalHDL/Simulation/clock.rst:99
 msgid "Execute the callback code only once on the next ``ClockDomain`` sample (active edge + reset off + clock enable on)"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:91
+#: ../../SpinalHDL/Simulation/clock.rst:100
 msgid "``onSamplings { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:92
+#: ../../SpinalHDL/Simulation/clock.rst:101
 msgid "Execute the callback code each time the ``ClockDomain`` sample (active edge + reset off + clock enable on)"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:93
+#: ../../SpinalHDL/Simulation/clock.rst:102
 msgid "``onActiveEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:94
+#: ../../SpinalHDL/Simulation/clock.rst:103
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates its configured edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:95
+#: ../../SpinalHDL/Simulation/clock.rst:104
 msgid "``onEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:96
+#: ../../SpinalHDL/Simulation/clock.rst:105
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising or falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:97
+#: ../../SpinalHDL/Simulation/clock.rst:106
 msgid "``onRisingEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:98
+#: ../../SpinalHDL/Simulation/clock.rst:107
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a rising edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:99
+#: ../../SpinalHDL/Simulation/clock.rst:108
 msgid "``onFallingEdges { callback }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:100
+#: ../../SpinalHDL/Simulation/clock.rst:109
 msgid "Execute the callback code each time the ``ClockDomain`` clock generates a falling edge"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:101
+#: ../../SpinalHDL/Simulation/clock.rst:110
 msgid "``onSamplingWhile { callback : Boolean }``"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:102
+#: ../../SpinalHDL/Simulation/clock.rst:111
 msgid "Same as onSampling, but you can stop it (forever) by letting the callback returning false"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:106
+#: ../../SpinalHDL/Simulation/clock.rst:115
 msgid "Default ClockDomain"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:108
+#: ../../SpinalHDL/Simulation/clock.rst:117
 msgid "You can access the default ``ClockDomain`` of your toplevel as shown below:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:124
+#: ../../SpinalHDL/Simulation/clock.rst:133
 msgid "Note that you can also directly fork a standard reset/clock process:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:130
+#: ../../SpinalHDL/Simulation/clock.rst:139
 msgid "An example of how to wait for a rising edge on the clock:"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:138
+#: ../../SpinalHDL/Simulation/clock.rst:147
 msgid "New ClockDomain"
 msgstr ""
 
-#: ../../SpinalHDL/Simulation/clock.rst:140
+#: ../../SpinalHDL/Simulation/clock.rst:149
 msgid "If your toplevel defines some clock and reset inputs which aren't directly integrated into their ``ClockDomain``, you can define their corresponding ``ClockDomain`` directly in the testbench:"
 msgstr ""