VHDL support in SpinalSim using GHDL as a backend

[eine]

While reading https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/, I wondered whether any effort has been done in order to replicate the workflow with VHDL sources. ghdl/ghdl can be used to compile VHDL files to C (shared) objects, just as Verilator is used with Verilog sources.

I am actually seeking to generate and compile a VHDL version of Murax SoC, to then simulate the execution of some of the example programs.

[Dolu1990]

Actualy, there is this interface in the spinal.sim sources :
https://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/SimRaw.scala#L15
which as to be implemented for a given target simulator
For Verilator it's implemented as following :
https://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/SimVerilator.scala
+
https://github.com/SpinalHDL/SpinalHDL/blob/master/sim/src/main/scala/spinal/sim/VerilatorBackend.scala

So in the case of verilator it wasn't a crazy amount of work. Then i have no idea how the ghdl shared object interface appear :)

[Dolu1990]

the def eval() function is called by spinalHDL to ask the simulatior to do delta cycles until everything is stabilized.
maybe that's a tricky thing ?

[eine]

Hi @Dolu1990! Thanks for the references.

I think that implementing something as eval() with GHDL might be possible with either the VPI or the VHPI interfaces. I have gathered some examples in 1138-4EB/hwd-ide/tree/vpi-ex-ghdl/examples, but I have not thoroughly learnt it yet.

I was looking for something 'easier' to start with. I tried the following for now:

• Replace generateVerilog and SpinalVerilog with generateVhdl and SpinalVhdl in VexRiscv/src/main/scala/vexriscv/demo/*.scala (see eine/VexRiscv@f9c7643).
  • As a result, 6 tests fail in travis: https://api.travis-ci.com/v3/job/145142296/log.txt
  • However, sbt "run-main vexriscv.demo.MuraxWithRamInit" generates a Murax.vhd file now.
• I created a VHDL testbench, using entity Murax in Murax.vhd as the UUT (see below).
• I can successfully analyze, elaborate and run both Murax.vhd and tb_murax.vhd:

ghdl_args="--std=08 -fPIC"
ghdl -a $ghdl_args Murax.vhd
ghdl -a $ghdl_args tb_murax.vhd
ghdl -e $ghdl_args tb_murax
./tb_murax --vcd=murax.vcd
gtkwave murax.vcd murax.gtkw

However, I don't know how to check it. The next step is to add a UART RX in the testbench, in order to read the output from Murax. But I am not sure about the clk period and the baud rate. I saw https://github.com/SpinalHDL/VexRiscv/blob/master/src/test/cpp/murax/main.cpp#L13-L16, so I think that the expected period might be 83.333 ns (12 MHz) and the baud rate 115200. Is this correct? Also, should I provide any default value to the unused input ports (io_jtag_tms, io_jtag_tdi, io_jtag_tck, io_gpioA_read and io_uart_rxd)?

---

Files

tb_murax.vhd:

library ieee;
context ieee.ieee_std_context;

entity tb_murax is
end entity;

architecture tb of tb_murax is
  constant clk_period: time := 83333 ps;
  signal io_asyncReset : std_logic;
  signal io_mainClk : std_logic := '0';
  signal io_jtag_tms : std_logic;
  signal io_jtag_tdi : std_logic;
  signal io_jtag_tdo : std_logic;
  signal io_jtag_tck : std_logic;
  signal io_gpioA_read : std_logic_vector(31 downto 0);
  signal io_gpioA_write : std_logic_vector(31 downto 0);
  signal io_gpioA_writeEnable : std_logic_vector(31 downto 0);
  signal io_uart_txd : std_logic;
  signal io_uart_rxd : std_logic;
begin
  io_mainClk <= not io_mainClk after clk_period/2;

  main: process begin
    io_asyncReset <= '1';
    wait for 15*clk_period;
    io_asyncReset <= '0';
    wait for 100 ms;
    report "End of simulation" severity failure;
    wait;
  end process;

  murax: entity work.Murax
    port map (
      io_asyncReset => io_asyncReset,
      io_mainClk => io_mainClk,
      io_jtag_tms => io_jtag_tms,
      io_jtag_tdi => io_jtag_tdi,
      io_jtag_tdo => io_jtag_tdo,
      io_jtag_tck => io_jtag_tck,
      io_gpioA_read => io_gpioA_read,
      io_gpioA_write => io_gpioA_write,
      io_gpioA_writeEnable => io_gpioA_writeEnable,
      io_uart_txd => io_uart_txd,
      io_uart_rxd => io_uart_rxd
    );
end architecture;

murax.gtkw:

[*]
[*] GTKWave Analyzer v3.3.95 (w)1999-2018 BSI
[*] Tue Sep 11 23:31:57 2018
[*]
[dumpfile] "/src/murax.vcd"
[dumpfile_mtime] "Tue Sep 11 23:06:04 2018"
[dumpfile_size] 195951776
[savefile] "/src/murax.gtkw"
[timestart] 0
[size] 1366 711
[pos] -1 -1
*-34.449421 25250000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_murax.
[treeopen] tb_murax.murax.
[treeopen] tb_murax.murax.system_cpu.
[treeopen] tb_murax.murax.system_uartctrl.uartctrl_1.
[sst_width] 210
[signals_width] 250
[sst_expanded] 1
[sst_vpaned_height] 279
@200
-tb_murax
@28
tb_murax.io_asyncreset
@22
tb_murax.io_gpioa_read[31:0]
@23
tb_murax.io_gpioa_write[31:0]
@22
tb_murax.io_gpioa_writeenable[31:0]
@28
tb_murax.io_jtag_tck
tb_murax.io_jtag_tdi
tb_murax.io_jtag_tdo
tb_murax.io_jtag_tms
tb_murax.io_mainclk
tb_murax.io_uart_rxd
tb_murax.io_uart_txd
@200
-system_uartctrl
@28
tb_murax.murax.system_uartctrl.io_uart_rxd
tb_murax.murax.system_uartctrl.io_uart_txd
tb_murax.murax.system_uartctrl.io_interrupt
tb_murax.murax.system_cpu.csrplugin_mstatus_mie
@200
-streamfifo_2
@22
tb_murax.murax.system_uartctrl.streamfifo_2.io_push_payload[7:0]
@28
tb_murax.murax.system_uartctrl.streamfifo_2.io_push_valid
tb_murax.murax.system_uartctrl.streamfifo_2.io_pop_valid
tb_murax.murax.system_uartctrl.streamfifo_2.io_pop_ready
@22
tb_murax.murax.system_uartctrl.streamfifo_2.io_pop_payload[7:0]
@200
-uartctrl_1
@22
tb_murax.murax.system_uartctrl.uartctrl_1.rx.io_read_payload[7:0]
@28
tb_murax.murax.system_uartctrl.uartctrl_1.rx.io_read_valid
@22
tb_murax.murax.system_uartctrl.uartctrl_1.rx.statemachine_shifter[7:0]
@28
tb_murax.murax.system_uartctrl.uartctrl_1.rx.bittimer_tick
tb_murax.murax.system_uartctrl.uartctrl_1.rx.bittimer_counter[2:0]
tb_murax.murax.system_uartctrl.uartctrl_1.rx.io_rxd
tb_murax.murax.system_uartctrl.uartctrl_1.rx.sampler_value
tb_murax.murax.system_uartctrl.uartctrl_1.rx.sampler_tick
tb_murax.murax.system_uartctrl.uartctrl_1.rx.sampler_samples_1
tb_murax.murax.system_uartctrl.uartctrl_1.rx.sampler_samples_2
[pattern_trace] 1
[pattern_trace] 0

[eine]

I tried adding UART RX and TX verification components to a VUnit testbench. So far it works ok. I could successfully write and get the same content out (as explained in SpinalHDL/VexRiscv#murax-soc). See testbench below:

I could also modify the demo program, rebuild it, and have it included when the SoC VHDL is generated.

@Dolu1990 , I am now looking at how to replace the UART with either AXI4 Stream interfaces or FIFOs. However, I did only find AXI4 Full and AXI4 Lite in https://github.com/SpinalHDL/SpinalHDL/tree/master/lib/src/main/scala/spinal/lib/bus. Am I missing any other source?

library ieee;
context ieee.ieee_std_context;

library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;

entity tb_murax is
  generic (
    runner_cfg : string);
end entity;

architecture tb of tb_murax is
  constant baud_rate : integer := 115200; -- bits / s
  constant clk_period: time := 83333 ps;

  signal asyncReset  : std_logic;
  signal mainClk     : std_logic := '0';
  signal jtag_tms    : std_logic;
  signal jtag_tdi    : std_logic;
  signal jtag_tdo    : std_logic;
  signal jtag_tck    : std_logic;
  signal gpioA_read  : std_logic_vector(31 downto 0);
  signal gpioA_write : std_logic_vector(31 downto 0);
  signal gpioA_writeEnable : std_logic_vector(31 downto 0);
  signal uart_txd    : std_logic;
  signal uart_rxd    : std_logic;

  constant tx_uart_bfm : uart_master_t := new_uart_master(initial_baud_rate => baud_rate);
  constant tx_stream : stream_master_t := as_stream(tx_uart_bfm);

  constant rx_uart_bfm : uart_slave_t := new_uart_slave(initial_baud_rate => baud_rate);
  constant rx_stream : stream_slave_t := as_stream(rx_uart_bfm);

begin

  mainClk <= not mainClk after (clk_period/2);

  main : process
    variable data : std_logic_vector(7 downto 0);
  begin
    test_runner_setup(runner, runner_cfg);
    while test_suite loop
      if run("test") then
        info("Init test");
        pop_stream(net, rx_stream, data);
        info(to_string(data));

        push_stream(net, tx_stream, x"77");

        pop_stream(net, rx_stream, data);
        info(to_string(data));

        push_stream(net, tx_stream, x"55");

        pop_stream(net, rx_stream, data);
        info(to_string(data));

        wait for 100 ms;
      end if;
    end loop;
    test_runner_cleanup(runner);
    wait;
  end process;
  test_runner_watchdog(runner, 100 ms);

  tx_bfm : entity vunit_lib.uart_master generic map ( uart => tx_uart_bfm ) port map ( tx => uart_rxd );
  rx_bfm : entity vunit_lib.uart_slave generic map  ( uart => rx_uart_bfm ) port map ( rx => uart_txd );

---

  murax: entity work.Murax
    port map (
      io_asyncReset  => asyncReset,
      io_mainClk     => mainClk,
      io_jtag_tms    => jtag_tms,
      io_jtag_tdi    => jtag_tdi,
      io_jtag_tdo    => jtag_tdo,
      io_jtag_tck    => jtag_tck,
      io_gpioA_read  => gpioA_read,
      io_gpioA_write => gpioA_write,
      io_gpioA_writeEnable => gpioA_writeEnable,
      io_uart_txd    => uart_txd,
      io_uart_rxd    => uart_rxd
    );

end architecture;

[Dolu1990]

@1138-4eb Sorry, i completly losed the track of this issue :/
Probably to interface other simulator, the good solution would be to do like cocotb, with VPI.

How things are going ?

[eine]

Hi @Dolu1990, thanks for pinging back! In the end, I did nothing with neither SpinalSim nor VPI. But I have successfully used GHDL, VUnit, VexRiscv and VHPI to run some simulations. The scheme is as follows:

• A module name Apb3Axis was added to Murax. These are two AXI Streams (a master and a slave) mapped to some registers in the VexRiscv memory space. See https://github.com/1138-4EB/VexRiscv/tree/add-axis.
• All the generateVerilog and SpinalVerilog statements were replaced with generateVhdl and SpinalVhdl. See https://github.com/1138-4EB/VexRiscv/tree/murax-vhdl-axis.
• A software routine was written in order to read data from the slave stream, do some arithmetic operations, and put the results back through the master stream.
• A VHDL testbench was written including: VexRiscv, VUnit UART verification components (RX and TX) and VUnit AXI Stream verification components (slave and master). Also, a companion C wrapper was written and some VHDL procedures were bind to C functions.

First, the RISCV software was built and the hex was generated. Then, the VHDL was generated with SpinalHDL. The VexRiscv VHDL and the testbench were compiled with GHDL. Last, a C app was built, adding the C wrapper and the compiled objects produced by GHDL.

When the app is started:

• Some memory is allocated and test data is randomly generated.
• GHDL is called internally as if it was any other function, and the simulation is started.
• During simulation, callbacks in C are executed to get data from the app memory space and put it in the slave AXI Stream (input to the RISCV). Consequently, callbacks are executed to get data back from the master AXI Stream (output from the RISCV) to the app memory space.
• When the simulation is finished, control is returned to the main app.

Moreover, all VHDL/VUnit logging features are available during simulation. Hence, execution statistics can be saved to log/csv files. Also, waveforms can be exported in any of the formats supported by GHDL, for further inspection with GUI tools, such as GtkWave.

Overall, it was some interesting investigation, as it is a useful setup to wrap GHDL in any other language that supports C-alike interfaces (say ada, golang, python, ruby, scala...).

However, I did not guess how to run the simulator only for the delta cycles corresponding to a timestamp, as you asked:

the def eval() function is called by spinalHDL to ask the simulatior to do delta cycles until everything is stabilized.
maybe that's a tricky thing ?

ATM, you call GHDL and the simulation runs until it is finished due to some assertion, error or because all the processes are stalled. I.e., the flow of the simulation is handled by GHDL.

Therefore, as you suggest,

Probably to interface other simulator, the good solution would be to do like cocotb, with VPI.

yes, VPI would probably be the best fit here. Unfortunately, I have no experience with it.

Nevertheless, I might have misunderstood the requirements for eval(). So, please, let me know if any of the info in this comment lights any bulb.

EDIT

ghdl/ghdl#154

[bellaz89]

Surfing around I found a useful resource:

https://essay.utwente.nl/70777/1/Verheij_MA_EEMCS.pdf

This is a master thesis on how the co-simulation between Clash and GHDL/ModelSim/Icarus was done.
C snippets are present in this thesis.

[bellaz89]

@eine
I created a frontend C++ library for GHDL. See https://github.com/bellaz89/GHDLInteropREPL. It should be enough for SpinalSim.

@Dolu1990
I realized that my library completely misses dealing with signed values. Should all three kinds (Int, Long, BigInt) be sign-extended when they are written on signals wider than their intrinsic bit site and vice-versa?

[Dolu1990]

@bellaz89 Hmmm, so far i remember the SpinalSim API threat numbers as raw data, so there is no difference between signed and unsigned numbers. So that's already fine as far i can see ^^

[eine]

@bellaz89, that's some interesting work. Thanks for the reference!

If going through the VPI path, you might find cocotb interesting. It uses either VPI or VHPI to interact with a bunch of simulators, GHDL being one of them.

For a more direct solution (with VHPIDIRECT/DPI), there is work in progress in VUnit/cosim. See also VUnit/vunit#603, ghdl/ghdl#1053 and ghdl/ghdl#1059. There are several comments about how to pass not only single values but also arrays or records/structs.

[bellaz89]

I have some updates.

I discovered that my previous approach didn't work because of the inability to link the entire GHDL runtime into a dynamic library.

Therefore I rewrote it (https://github.com/bellaz89/VPIInteropREPL). This project uses boost-interprocess to communicate between the simulator and the client program.
Such an interface is a much cleaner approach than the older one and it allows to simulate with ghdl-mcode and icarus verilog. With minimal effort It could be possible to add the support of other (commercial) simulators that use VPI. Since the interfacing code doesn't change from simulation to simulation we can think about caching the modules and libraries for later use to speed up the simulations.

[bellaz89]

@Dolu1990

In #293 I did the following things:

1. Added a generic VPI backend with shared memory communication. This is done using boost-interprocess
2. Added support to GHDL and its three flavors (mcode/gcc/llvm)
3. Added support to Icarus Verilog
4. Added support to GHDL wave files
5. Written SimVPI and modified Signal adding an initialization flag and extending the id to Long

I am able to run simulations nicely in scala with

sbt "sim/test:runMain spinal.sim.PlayGhdl"

You need to have Icarus Verilog or GHDL in your path and boost/interprocess headers in your include path.

See https://github.com/bellaz89/SpinalHDL/blob/ee3bb11415b337bfb4614cffe0957d7ea070e9a8/sim/src/test/scala/spinal/sim/Test2.scala#L62 and https://github.com/bellaz89/SpinalHDL/blob/ee3bb11415b337bfb4614cffe0957d7ea070e9a8/sim/src/test/scala/spinal/sim/Test2.scala#L95

Either sim/yolo/adder.vhd or sim/yolo/adder.v are used for the test.
The backend code creates the JNI shared library and the VPI plugins in sim/simulation_plugins/.
Since both JNI and VPI objects don't change from simulation to simulation, they are re-used by the following simulations significantly speeding up the loading time.

Remaining tasks/ideas

• Adding an user interface to manage the new simulators and their parameters.
• Test/adapt the code on windows/macos machines
• Stress test the backends (Vexriscv simulations? SpinalHDL test suite?)
• Adding a SpinalSim flag to automatically pick the 'best' simulator using the installed simulators/rtl files extensions as information
• Add support of IVerilator wave files. May this involve modification in how the top entity code is generated? See https://iverilog.fandom.com/wiki/GTKWAVE and Specify dumpfile via command line? steveicarus/iverilog#202
• Might it be useful to run GHDL in parallel along with Verilator/ IVerilog to cross-check SpinalHDL's vhdl and verilog generators?
• Documenting everything

Update
Due to incompatibilities between SpinalSim and IVerilog execution model, the IVerilog backend is not working properly anymore. See #295 .

Update

Now Icarus Verilog backend works as it should