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facebreezefacebreeze
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update deprecated Bool to Bool()
1 parent 6807560 commit ae164c3

15 files changed

Lines changed: 69 additions & 69 deletions

‎doc/gcdPeripheral/src/main/scala/vexriscv/periph/gcd/GCDTop.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,13 +5,13 @@ import spinal.lib._
55
import spinal.lib.IMasterSlave
66

77
case class GCDDataControl() extends Bundle with IMasterSlave{
8-
val cmpAgtB = Bool
9-
val cmpAltB = Bool
10-
val loadA = Bool
11-
val loadB = Bool
12-
val init = Bool
13-
val selL = Bool
14-
val selR = Bool
8+
val cmpAgtB = Bool()
9+
val cmpAltB = Bool()
10+
val loadA = Bool()
11+
val loadB = Bool()
12+
val init = Bool()
13+
val selL = Bool()
14+
val selR = Bool()
1515
// define <> semantic
1616
override def asMaster(): Unit = {
1717
// as controller: output, input

‎src/main/scala/vexriscv/Services.scala‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -89,19 +89,19 @@ trait RegFileService{
8989

9090

9191
case class MemoryTranslatorCmd() extends Bundle{
92-
val isValid = Bool
93-
val isStuck = Bool
92+
val isValid = Bool()
93+
val isStuck = Bool()
9494
val virtualAddress = UInt(32 bits)
95-
val bypassTranslation = Bool
95+
val bypassTranslation = Bool()
9696
}
9797
case class MemoryTranslatorRsp(p : MemoryTranslatorBusParameter) extends Bundle{
9898
val physicalAddress = UInt(32 bits)
99-
val isIoAccess = Bool
100-
val isPaging = Bool
101-
val allowRead, allowWrite, allowExecute = Bool
102-
val exception = Bool
103-
val refilling = Bool
104-
val bypassTranslation = Bool
99+
val isIoAccess = Bool()
100+
val isPaging = Bool()
101+
val allowRead, allowWrite, allowExecute = Bool()
102+
val exception = Bool()
103+
val refilling = Bool()
104+
val bypassTranslation = Bool()
105105
val ways = Vec(MemoryTranslatorRspWay(), p.wayCount)
106106
}
107107
case class MemoryTranslatorRspWay() extends Bundle{
@@ -113,8 +113,8 @@ case class MemoryTranslatorBusParameter(wayCount : Int = 0, latency : Int = 0)
113113
case class MemoryTranslatorBus(p : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
114114
val cmd = Vec(MemoryTranslatorCmd(), p.latency + 1)
115115
val rsp = MemoryTranslatorRsp(p)
116-
val end = Bool
117-
val busy = Bool
116+
val end = Bool()
117+
val busy = Bool()
118118

119119
override def asMaster() : Unit = {
120120
out(cmd, end)

‎src/main/scala/vexriscv/Stage.scala‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -51,13 +51,13 @@ class Stage() extends Area{
5151
val removeIt = False //When settable, unschedule the instruction as if it was never executed (no side effect)
5252
val flushIt = False //When settable, unschedule the current instruction
5353
val flushNext = False //When settable, unschedule instruction above in the pipeline
54-
val isValid = Bool //Inform if a instruction is in the current stage
55-
val isStuck = Bool //Inform if the instruction is stuck (haltItself || haltByOther)
56-
val isStuckByOthers = Bool //Inform if the instruction is stuck by sombody else
54+
val isValid = Bool() //Inform if a instruction is in the current stage
55+
val isStuck = Bool() //Inform if the instruction is stuck (haltItself || haltByOther)
56+
val isStuckByOthers = Bool() //Inform if the instruction is stuck by sombody else
5757
def isRemoved = removeIt //Inform if the instruction is going to be unschedule the current cycle
58-
val isFlushed = Bool //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
59-
val isMoving = Bool //Inform if the instruction is going somewere else (next stage or unscheduled)
60-
val isFiring = Bool //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
58+
val isFlushed = Bool() //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
59+
val isMoving = Bool() //Inform if the instruction is going somewere else (next stage or unscheduled)
60+
val isFiring = Bool() //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
6161
}
6262

6363

‎src/main/scala/vexriscv/ip/DataCache.scala‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -118,11 +118,11 @@ object DataCacheCpuExecute{
118118
}
119119

120120
case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterSlave{
121-
val isValid = Bool
121+
val isValid = Bool()
122122
val address = UInt(p.addressWidth bit)
123-
val haltIt = Bool
123+
val haltIt = Bool()
124124
val args = DataCacheCpuExecuteArgs(p)
125-
val refilling = Bool
125+
val refilling = Bool()
126126

127127
override def asMaster(): Unit = {
128128
out(isValid, args, address)
@@ -131,7 +131,7 @@ case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterS
131131
}
132132

133133
case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
134-
val wr = Bool
134+
val wr = Bool()
135135
val size = UInt(log2Up(log2Up(p.cpuDataBytes)+1) bits)
136136
val isLrsc = p.withLrSc generate Bool()
137137
val isAmo = p.withAmo generate Bool()
@@ -144,9 +144,9 @@ case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
144144
}
145145

146146
case class DataCacheCpuMemory(p : DataCacheConfig, mmu : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
147-
val isValid = Bool
148-
val isStuck = Bool
149-
val isWrite = Bool
147+
val isValid = Bool()
148+
val isStuck = Bool()
149+
val isWrite = Bool()
150150
val address = UInt(p.addressWidth bit)
151151
val mmuRsp = MemoryTranslatorRsp(mmu)
152152

@@ -222,14 +222,14 @@ case class DataCacheCpuBus(p : DataCacheConfig, mmu : MemoryTranslatorBusParamet
222222

223223

224224
case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
225-
val wr = Bool
226-
val uncached = Bool
225+
val wr = Bool()
226+
val uncached = Bool()
227227
val address = UInt(p.addressWidth bit)
228228
val data = Bits(p.cpuDataWidth bits)
229229
val mask = Bits(p.cpuDataWidth/8 bits)
230230
val size = UInt(p.sizeWidth bits) //... 1 => 2 bytes ... 2 => 4 bytes ...
231231
val exclusive = p.withExclusive generate Bool()
232-
val last = Bool
232+
val last = Bool()
233233

234234
// def beatCountMinusOne = size.muxListDc((0 to p.sizeMax).map(i => i -> U((1 << i)/p.memDataBytes)))
235235
// def beatCount = size.muxListDc((0 to p.sizeMax).map(i => i -> U((1 << i)/p.memDataBytes-1)))
@@ -244,7 +244,7 @@ case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
244244
val aggregated = UInt(p.aggregationWidth bits)
245245
val last = Bool()
246246
val data = Bits(p.memDataWidth bit)
247-
val error = Bool
247+
val error = Bool()
248248
val exclusive = p.withExclusive generate Bool()
249249
}
250250
case class DataCacheInv(p : DataCacheConfig) extends Bundle{
@@ -708,7 +708,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
708708
io.mem.sync.ready := True
709709
val syncCount = io.mem.sync.aggregated +^ 1
710710
val syncContext = new Area{
711-
val history = Mem(Bool, pendingMax)
711+
val history = Mem(Bool(), pendingMax)
712712
val wPtr, rPtr = Reg(UInt(log2Up(pendingMax)+1 bits)) init(0)
713713
when(io.mem.cmd.fire && io.mem.cmd.wr){
714714
history.write(wPtr.resized, io.mem.cmd.uncached)

‎src/main/scala/vexriscv/ip/InstructionCache.scala‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -88,8 +88,8 @@ case class InstructionCacheConfig( cacheSize : Int,
8888

8989

9090
case class InstructionCacheCpuPrefetch(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
91-
val isValid = Bool
92-
val haltIt = Bool
91+
val isValid = Bool()
92+
val haltIt = Bool()
9393
val pc = UInt(p.addressWidth bit)
9494

9595
override def asMaster(): Unit = {
@@ -129,8 +129,8 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig, mmuParameter : M
129129

130130

131131
case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle with IMasterSlave with InstructionCacheCommons {
132-
val isValid = Bool
133-
val isStuck = Bool
132+
val isValid = Bool()
133+
val isStuck = Bool()
134134
val pc = UInt(p.addressWidth bits)
135135
val physicalAddress = UInt(p.addressWidth bits)
136136
val data = Bits(p.cpuDataWidth bits)
@@ -161,7 +161,7 @@ case class InstructionCacheMemCmd(p : InstructionCacheConfig) extends Bundle{
161161

162162
case class InstructionCacheMemRsp(p : InstructionCacheConfig) extends Bundle{
163163
val data = Bits(p.memDataWidth bit)
164-
val error = Bool
164+
val error = Bool()
165165
}
166166

167167
case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
@@ -271,7 +271,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
271271

272272
case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{
273273
val cmd = Event
274-
val rsp = Bool
274+
val rsp = Bool()
275275

276276
override def asMaster(): Unit = {
277277
master(cmd)
@@ -298,8 +298,8 @@ class InstructionCache(p : InstructionCacheConfig, mmuParameter : MemoryTranslat
298298
val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
299299

300300
case class LineTag() extends Bundle{
301-
val valid = Bool
302-
val error = Bool
301+
val valid = Bool()
302+
val error = Bool()
303303
val address = UInt(tagRange.length bit)
304304
}
305305

‎src/main/scala/vexriscv/ip/fpu/FpuCore.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
172172
}
173173

174174
val scoreboards = Array.fill(portCount)(new Area{
175-
val target, hit = Mem(Bool, 32) // XOR
176-
val writes = Mem(Bool, 32)
175+
val target, hit = Mem(Bool(), 32) // XOR
176+
val writes = Mem(Bool(), 32)
177177

178178
val targetWrite = init(target.writePort)
179179
val hitWrite = init(hit.writePort)

‎src/main/scala/vexriscv/plugin/BranchPlugin.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,22 +18,22 @@ object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
1818

1919

2020
case class DecodePredictionCmd() extends Bundle {
21-
val hadBranch = Bool
21+
val hadBranch = Bool()
2222
}
2323
case class DecodePredictionRsp(stage : Stage) extends Bundle {
24-
val wasWrong = Bool
24+
val wasWrong = Bool()
2525
}
2626
case class DecodePredictionBus(stage : Stage) extends Bundle {
2727
val cmd = DecodePredictionCmd()
2828
val rsp = DecodePredictionRsp(stage)
2929
}
3030

3131
case class FetchPredictionCmd() extends Bundle{
32-
val hadBranch = Bool
32+
val hadBranch = Bool()
3333
val targetPc = UInt(32 bits)
3434
}
3535
case class FetchPredictionRsp() extends Bundle{
36-
val wasRight = Bool
36+
val wasRight = Bool()
3737
val finalPc = UInt(32 bits)
3838
val sourceLastWord = UInt(32 bits)
3939
}

‎src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,16 +15,16 @@ import scala.collection.mutable.ArrayBuffer
1515

1616

1717
case class DBusSimpleCmd() extends Bundle{
18-
val wr = Bool
18+
val wr = Bool()
1919
val mask = Bits(4 bit)
2020
val address = UInt(32 bits)
2121
val data = Bits(32 bit)
2222
val size = UInt(2 bit)
2323
}
2424

2525
case class DBusSimpleRsp() extends Bundle with IMasterSlave{
26-
val ready = Bool
27-
val error = Bool
26+
val ready = Bool()
27+
val error = Bool()
2828
val data = Bits(32 bit)
2929

3030
override def asMaster(): Unit = {

‎src/main/scala/vexriscv/plugin/DebugPlugin.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ import scala.collection.mutable.ArrayBuffer
1717

1818

1919
case class DebugExtensionCmd() extends Bundle{
20-
val wr = Bool
20+
val wr = Bool()
2121
val address = UInt(8 bit)
2222
val data = Bits(32 bit)
2323
}
@@ -182,7 +182,7 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
182182

183183
case class DebugExtensionIo() extends Bundle with IMasterSlave{
184184
val bus = DebugExtensionBus()
185-
val resetOut = Bool
185+
val resetOut = Bool()
186186

187187
override def asMaster(): Unit = {
188188
master(bus)

‎src/main/scala/vexriscv/plugin/Fetcher.scala‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -483,7 +483,7 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
483483
val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
484484

485485
case class DynamicContext() extends Bundle{
486-
val hazard = Bool
486+
val hazard = Bool()
487487
val line = BranchPredictorLine()
488488
}
489489
val fetchContext = DynamicContext()
@@ -539,7 +539,7 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
539539
case class BranchPredictorLine() extends Bundle{
540540
val source = Bits(30 - historyRamSizeLog2 bits)
541541
val branchWish = UInt(2 bits)
542-
val last2Bytes = ifGen(compressedGen)(Bool)
542+
val last2Bytes = ifGen(compressedGen)(Bool())
543543
val target = UInt(32 bits)
544544
}
545545

@@ -576,8 +576,8 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
576576
fetchPc.predictionPcLoad.payload := line.target
577577

578578
case class PredictionResult() extends Bundle{
579-
val hazard = Bool
580-
val hit = Bool
579+
val hazard = Bool()
580+
val hit = Bool()
581581
val line = BranchPredictorLine()
582582
}
583583

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