update deprecated Bool to Bool()

doc/gcdPeripheral/src/main/scala/vexriscv/periph/gcd/GCDTop.scala

@@ -5,13 +5,13 @@ import spinal.lib._
 import spinal.lib.IMasterSlave
 
 case class GCDDataControl() extends Bundle with IMasterSlave{
-  val cmpAgtB = Bool
-  val cmpAltB = Bool
-  val loadA = Bool
-  val loadB = Bool
-  val init = Bool
-  val selL = Bool
-  val selR = Bool
+  val cmpAgtB = Bool()
+  val cmpAltB = Bool()
+  val loadA = Bool()
+  val loadB = Bool()
+  val init = Bool()
+  val selL = Bool()
+  val selR = Bool()
   // define <> semantic
   override def asMaster(): Unit = {
     // as controller: output, input

src/main/scala/vexriscv/Services.scala

@@ -89,19 +89,19 @@ trait RegFileService{
 
 
 case class MemoryTranslatorCmd() extends Bundle{
-  val isValid = Bool
-  val isStuck = Bool
+  val isValid = Bool()
+  val isStuck = Bool()
   val virtualAddress  = UInt(32 bits)
-  val bypassTranslation = Bool
+  val bypassTranslation = Bool()
 }
 case class MemoryTranslatorRsp(p : MemoryTranslatorBusParameter) extends Bundle{
   val physicalAddress = UInt(32 bits)
-  val isIoAccess = Bool
-  val isPaging = Bool
-  val allowRead, allowWrite, allowExecute = Bool
-  val exception = Bool
-  val refilling = Bool
-  val bypassTranslation = Bool
+  val isIoAccess = Bool()
+  val isPaging = Bool()
+  val allowRead, allowWrite, allowExecute = Bool()
+  val exception = Bool()
+  val refilling = Bool()
+  val bypassTranslation = Bool()
   val ways = Vec(MemoryTranslatorRspWay(), p.wayCount)
 }
 case class MemoryTranslatorRspWay() extends Bundle{
@@ -113,8 +113,8 @@ case class MemoryTranslatorBusParameter(wayCount : Int = 0, latency : Int = 0)
 case class MemoryTranslatorBus(p : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
   val cmd = Vec(MemoryTranslatorCmd(), p.latency + 1)
   val rsp = MemoryTranslatorRsp(p)
-  val end = Bool
-  val busy = Bool
+  val end = Bool()
+  val busy = Bool()
 
   override def asMaster() : Unit = {
     out(cmd, end)

src/main/scala/vexriscv/Stage.scala

@@ -51,13 +51,13 @@ class Stage() extends Area{
     val removeIt    = False   //When settable, unschedule the instruction as if it was never executed (no side effect)
     val flushIt    = False   //When settable, unschedule the current instruction
     val flushNext    = False   //When settable, unschedule instruction above in the pipeline
-    val isValid     = Bool //Inform if a instruction is in the current stage
-    val isStuck     = Bool           //Inform if the instruction is stuck (haltItself || haltByOther)
-    val isStuckByOthers = Bool       //Inform if the instruction is stuck by sombody else
+    val isValid     = Bool() //Inform if a instruction is in the current stage
+    val isStuck     = Bool()           //Inform if the instruction is stuck (haltItself || haltByOther)
+    val isStuckByOthers = Bool()       //Inform if the instruction is stuck by sombody else
     def isRemoved   = removeIt       //Inform if the instruction is going to be unschedule the current cycle
-    val isFlushed   = Bool           //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
-    val isMoving     = Bool           //Inform if the instruction is going somewere else (next stage or unscheduled)
-    val isFiring    = Bool           //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
+    val isFlushed   = Bool()           //Inform if the instruction is flushed (flushAll set in the current or subsequents stages)
+    val isMoving     = Bool()           //Inform if the instruction is going somewere else (next stage or unscheduled)
+    val isFiring    = Bool()           //Inform if the current instruction will go to the next stage the next cycle (isValid && !isStuck && !removeIt)
   }
 
 

src/main/scala/vexriscv/ip/DataCache.scala

@@ -118,11 +118,11 @@ object DataCacheCpuExecute{
 }
 
 case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterSlave{
-  val isValid = Bool
+  val isValid = Bool()
   val address = UInt(p.addressWidth bit)
-  val haltIt = Bool
+  val haltIt = Bool()
   val args = DataCacheCpuExecuteArgs(p)
-  val refilling = Bool
+  val refilling = Bool()
 
   override def asMaster(): Unit = {
     out(isValid, args, address)
@@ -131,7 +131,7 @@ case class DataCacheCpuExecute(p : DataCacheConfig) extends Bundle with IMasterS
 }
 
 case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
-  val wr = Bool
+  val wr = Bool()
   val size = UInt(log2Up(log2Up(p.cpuDataBytes)+1) bits)
   val isLrsc = p.withLrSc generate Bool()
   val isAmo = p.withAmo generate Bool()
@@ -144,9 +144,9 @@ case class DataCacheCpuExecuteArgs(p : DataCacheConfig) extends Bundle{
 }
 
 case class DataCacheCpuMemory(p : DataCacheConfig, mmu : MemoryTranslatorBusParameter) extends Bundle with IMasterSlave{
-  val isValid = Bool
-  val isStuck = Bool
-  val isWrite = Bool
+  val isValid = Bool()
+  val isStuck = Bool()
+  val isWrite = Bool()
   val address = UInt(p.addressWidth bit)
   val mmuRsp  = MemoryTranslatorRsp(mmu)
 
@@ -222,14 +222,14 @@ case class DataCacheCpuBus(p : DataCacheConfig, mmu : MemoryTranslatorBusParamet
 
 
 case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
-  val wr = Bool
-  val uncached = Bool
+  val wr = Bool()
+  val uncached = Bool()
   val address = UInt(p.addressWidth bit)
   val data = Bits(p.cpuDataWidth bits)
   val mask = Bits(p.cpuDataWidth/8 bits)
   val size   = UInt(p.sizeWidth bits) //... 1 => 2 bytes ... 2 => 4 bytes ...
   val exclusive = p.withExclusive generate Bool()
-  val last = Bool
+  val last = Bool()
 
 //  def beatCountMinusOne = size.muxListDc((0 to p.sizeMax).map(i => i -> U((1 << i)/p.memDataBytes)))
 //  def beatCount = size.muxListDc((0 to p.sizeMax).map(i => i -> U((1 << i)/p.memDataBytes-1)))
@@ -244,7 +244,7 @@ case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
   val aggregated = UInt(p.aggregationWidth bits)
   val last = Bool()
   val data = Bits(p.memDataWidth bit)
-  val error = Bool
+  val error = Bool()
   val exclusive = p.withExclusive generate Bool()
 }
 case class DataCacheInv(p : DataCacheConfig) extends Bundle{
@@ -708,7 +708,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
     io.mem.sync.ready := True
     val syncCount = io.mem.sync.aggregated +^ 1
     val syncContext = new Area{
-      val history = Mem(Bool, pendingMax)
+      val history = Mem(Bool(), pendingMax)
       val wPtr, rPtr = Reg(UInt(log2Up(pendingMax)+1 bits)) init(0)
       when(io.mem.cmd.fire && io.mem.cmd.wr){
         history.write(wPtr.resized, io.mem.cmd.uncached)

src/main/scala/vexriscv/ip/InstructionCache.scala

@@ -88,8 +88,8 @@ case class InstructionCacheConfig( cacheSize : Int,
 
 
 case class InstructionCacheCpuPrefetch(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
-  val isValid  = Bool
-  val haltIt   = Bool
+  val isValid  = Bool()
+  val haltIt   = Bool()
   val pc  = UInt(p.addressWidth bit)
 
   override def asMaster(): Unit = {
@@ -129,8 +129,8 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig, mmuParameter : M
 
 
 case class InstructionCacheCpuDecode(p : InstructionCacheConfig) extends Bundle with IMasterSlave with InstructionCacheCommons {
-  val isValid = Bool
-  val isStuck  = Bool
+  val isValid = Bool()
+  val isStuck  = Bool()
   val pc = UInt(p.addressWidth bits)
   val physicalAddress = UInt(p.addressWidth bits)
   val data  =  Bits(p.cpuDataWidth bits)
@@ -161,7 +161,7 @@ case class InstructionCacheMemCmd(p : InstructionCacheConfig) extends Bundle{
 
 case class InstructionCacheMemRsp(p : InstructionCacheConfig) extends Bundle{
   val data = Bits(p.memDataWidth bit)
-  val error = Bool
+  val error = Bool()
 }
 
 case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
@@ -271,7 +271,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
 
 case class InstructionCacheFlushBus() extends Bundle with IMasterSlave{
   val cmd = Event
-  val rsp = Bool
+  val rsp = Bool()
 
   override def asMaster(): Unit = {
     master(cmd)
@@ -298,8 +298,8 @@ class InstructionCache(p : InstructionCacheConfig, mmuParameter : MemoryTranslat
   val lineRange = tagRange.low-1 downto log2Up(bytePerLine)
 
   case class LineTag() extends Bundle{
-    val valid = Bool
-    val error = Bool
+    val valid = Bool()
+    val error = Bool()
     val address = UInt(tagRange.length bit)
   }
 

src/main/scala/vexriscv/ip/fpu/FpuCore.scala

@@ -172,8 +172,8 @@ case class FpuCore( portCount : Int, p : FpuParameter) extends Component{
     }
 
     val scoreboards = Array.fill(portCount)(new Area{
-      val target, hit = Mem(Bool, 32) // XOR
-      val writes = Mem(Bool, 32)
+      val target, hit = Mem(Bool(), 32) // XOR
+      val writes = Mem(Bool(), 32)
 
       val targetWrite = init(target.writePort)
       val hitWrite = init(hit.writePort)

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -18,22 +18,22 @@ object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
 
 
 case class DecodePredictionCmd() extends Bundle {
-  val hadBranch = Bool
+  val hadBranch = Bool()
 }
 case class DecodePredictionRsp(stage : Stage) extends Bundle {
-  val wasWrong = Bool
+  val wasWrong = Bool()
 }
 case class DecodePredictionBus(stage : Stage) extends Bundle {
   val cmd = DecodePredictionCmd()
   val rsp = DecodePredictionRsp(stage)
 }
 
 case class FetchPredictionCmd() extends Bundle{
-  val hadBranch = Bool
+  val hadBranch = Bool()
   val targetPc = UInt(32 bits)
 }
 case class FetchPredictionRsp() extends Bundle{
-  val wasRight = Bool
+  val wasRight = Bool()
   val finalPc = UInt(32 bits)
   val sourceLastWord = UInt(32 bits)
 }

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -15,16 +15,16 @@ import scala.collection.mutable.ArrayBuffer
 
 
 case class DBusSimpleCmd() extends Bundle{
-  val wr = Bool
+  val wr = Bool()
   val mask = Bits(4 bit)
   val address = UInt(32 bits)
   val data = Bits(32 bit)
   val size = UInt(2 bit)
 }
 
 case class DBusSimpleRsp() extends Bundle with IMasterSlave{
-  val ready = Bool
-  val error = Bool
+  val ready = Bool()
+  val error = Bool()
   val data = Bits(32 bit)
 
   override def asMaster(): Unit = {

src/main/scala/vexriscv/plugin/DebugPlugin.scala

@@ -17,7 +17,7 @@ import scala.collection.mutable.ArrayBuffer
 
 
 case class DebugExtensionCmd() extends Bundle{
-  val wr = Bool
+  val wr = Bool()
   val address = UInt(8 bit)
   val data = Bits(32 bit)
 }
@@ -182,7 +182,7 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
 
 case class DebugExtensionIo() extends Bundle with IMasterSlave{
   val bus = DebugExtensionBus()
-  val resetOut = Bool
+  val resetOut = Bool()
 
   override def asMaster(): Unit = {
     master(bus)

src/main/scala/vexriscv/plugin/Fetcher.scala

@@ -483,7 +483,7 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
           val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(0).input.payload >> 2).resized
 
           case class DynamicContext() extends Bundle{
-            val hazard = Bool
+            val hazard = Bool()
             val line = BranchPredictorLine()
           }
           val fetchContext = DynamicContext()
@@ -539,7 +539,7 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
         case class BranchPredictorLine()  extends Bundle{
           val source = Bits(30 - historyRamSizeLog2 bits)
           val branchWish = UInt(2 bits)
-          val last2Bytes = ifGen(compressedGen)(Bool)
+          val last2Bytes = ifGen(compressedGen)(Bool())
           val target = UInt(32 bits)
         }
 
@@ -576,8 +576,8 @@ abstract class IBusFetcherImpl(var resetVector : BigInt,
         fetchPc.predictionPcLoad.payload := line.target
 
         case class PredictionResult()  extends Bundle{
-          val hazard = Bool
-          val hit = Bool
+          val hazard = Bool()
+          val hit = Bool()
           val line = BranchPredictorLine()
         }
 

src/main/scala/vexriscv/plugin/FormalPlugin.scala

@@ -29,12 +29,12 @@ case class RvfiPortMem() extends Bundle{
 }
 
 case class RvfiPort() extends Bundle with IMasterSlave {
-  val valid = Bool
+  val valid = Bool()
   val order = UInt(64 bits)
   val insn = Bits(32 bits)
-  val trap = Bool
-  val halt = Bool
-  val intr = Bool
+  val trap = Bool()
+  val halt = Bool()
+  val intr = Bool()
   val mode = Bits(2 bits)
   val ixl = Bits(2 bits)
   val rs1 = RvfiPortRsRead()

src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala

@@ -17,7 +17,7 @@ case class IBusSimpleCmd() extends Bundle{
 }
 
 case class IBusSimpleRsp() extends Bundle with IMasterSlave{
-  val error = Bool
+  val error = Bool()
   val inst  = Bits(32 bits)
 
   override def asMaster(): Unit = {

src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala

@@ -28,7 +28,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
     port.bus
   }
 
-  object IS_TLB extends Stageable(Bool)
+  object IS_TLB extends Stageable(Bool())
   override def setup(pipeline: VexRiscv): Unit = {
     import Riscv._
     import pipeline.config._
@@ -49,10 +49,10 @@ class MemoryTranslatorPlugin(tlbSize : Int,
     val sortedPortsInfo = portsInfo.sortWith((a,b) => a.priority > b.priority)
 
     case class CacheLine() extends Bundle {
-      val valid = Bool
+      val valid = Bool()
       val virtualAddress = UInt(20 bits)
       val physicalAddress = UInt(20 bits)
-      val allowRead, allowWrite, allowExecute, allowUser = Bool
+      val allowRead, allowWrite, allowExecute, allowUser = Bool()
 
       def init = {
         valid init (False)

src/main/scala/vexriscv/plugin/MmuPlugin.scala

@@ -13,7 +13,7 @@ trait DBusAccessService{
 case class DBusAccessCmd() extends Bundle {
   val address = UInt(32 bits)
   val size = UInt(2 bits)
-  val write = Bool
+  val write = Bool()
   val data = Bits(32 bits)
   val writeMask = Bits(4 bits)
 }

src/main/scala/vexriscv/plugin/PmpPlugin.scala

@@ -81,7 +81,7 @@ case class PmpRegister(previous : PmpRegister) extends Area {
   // registers. This makes locking and WARL possible.
   val csr = new Area {
     val r, w, x = Bool
-    val l = Bool
+    val l = Bool()
     val a = UInt(2 bits)
     val addr = UInt(32 bits)
   }