4MB firmware (v1 & v2)

[avelor-76]

In the project README, you say: ”For the 4 MB version, solder U7 and U8 only and use the dedicated firmware.”
This seems to be valid for the v2 firmware source (only RAS2 and RAS3 used, when 4MB is defined).

However, for v1 firmware it is the opposite, if I understand well the code: comments indicate to remove the case statements corresponding to RAS2 and RAS3. Hence I would believe RAS0 and RAS1 are used in this case. So 4Mb version of v1 firmware would require to solder U5 and U6, correct?

[SukkoPera]

Good point, but if I wrote that, I probably tested it, I can't remember.

Note that the signal names in the sources don't necessarily map to the corresponding signals in the schematics. I think it depends of the .pof file.

Let me know if you find out.

[avelor-76]

Ok, I will do some tests in the coming weeks and let you know.

[avelor-76]

Unfortunately I cannot test the V1 binary epm7032slc44-10.pof, because I only have epm7064 devices.
Maybe when compiling the pof file, RAS0 and RAS1 signals in the V1 source have been mapped to RAS2 and RAS3 PINs in the Quartus Assignment editor? I can't tell, as there isn't a qsf file in the source dir.
However, I will try to get epm7032 later and test again.

Now I am trying to compile the 4MB V1 version for my epm7064 following instructions in "FIRMWARE.txt".
I am using Quartus II v13.0.1.232 (the last one supporting 7000S device). I can't easily find Quartus 7.2 for download.

I have a few questions (sorry, I haven't got much experience with Quartus before):

1. I get a critical warning about missing SDC file, that - if I understood it well - is used to define the clock frequency for the design. This produces another critical warning: "Timing requirements not met".
   Do you have any suggestion on how to create a proper SDC file for the project?

2. Instructions mention to set all output pins as "slow slew rate" in assignment editor. Does this mean "output pins" only, or "input/output" pins (d12, d13, d14, d15) as well?
   After setting this, the corresponding lines in the qsf file are:
   set_instance_assignment -name SLOW_SLEW_RATE ON -to [output pin]
   Is this correct?

3. I'd like to generate a "no_autoconfig" version as well, that seems quite useful to debug bad memory chips.
   What I would do is changing line 260 of the verilog code:

   OpenAmiga500FastRamExpansion/firmware/V1/source/a600_8mb.v

   Lines 259 to 265 in ef0caab

   	if( cpu_nreset==0 ) // reset - begin autoconf
   	autoconf_on <= 1;
   	else
   	begin
   	if( high_addr==8'hE8 && low_addr[5:2]==4'b1001 ) // $E80048..$E8004E
   	autoconf_on <= 0;
   	end

   
   and have autoconf_on <= 0; instead of autoconf_on <= 1;. Would that make sense?

[SukkoPera]

Unfortunately I cannot help with any of your questions. I had no role in the development of the firmware and I even have no experience at all with Quartus, I'm sorry.

One thing I checked though regards the original question: the A600 version of this is only 4 MB in order to avoid conflicts with the PCMCIA address space and the 2 RAM chips there are connected to RAS2 and RAS3. Since the firmware is the same I think my original recommendation here is correct.

[avelor-76]

Hi, thanks! Indeed, I also checked the Amiga600 schematics before, and found it is consistent with your original recommendation (and with source code of firmware version V2).
By the way, I haven't seen a 4MB binary of firmware version V2 in the repository.
Does it mean that one should use the V1 binary for Amiga600 (or a self-compiled V2 changing the code for 4MB)?

In the meanwhile, I found an answer for my question 2), by looking at this project: https://github.com/lvd2/A600_8mb_2008/ .
The firmware there is derived from the same original project by lvd.
The repository contains a qsf file with similar assignments for all output pins, including "input/output" pins (d12, d13, d14, d15).

About question 1), I could remove critical warnings by adding a SDC file containing this single line:
derive_clocks -period 125
using 125 ns period => 8MHz. Not sure this single line is enough though.

I see firmware commits are by @LIV2, do you think he can help with the remaining questions? Or maybe I can try to contact the original author lvd?
If you want, once I come out with a proper Quartus setup, I can add the info and/or Quartus project files to the repository, for helping other people that might want to recompile the firmware.

I currently get a green screen at boot, not sure this is because of something wrong in my self-compiled firmware or an hardware issue...

[LIV2]

Re: RAS lines it's possible I made a mistake when implementing the v2 firmware and got that backwards - I thought I tested that at the time but it's been a while and I don't remember

Since the .qsf of the original firmware is missing i am not sure if perhaps the pin mapping is different from that - I can experiment more in a couple of weeks (I just moved around the world and my stuff isn't here yet)

Re: No Autoconfig, 4MB V2, Slew I can help with that in a few days when i'm near a computer again

[LIV2]

The readme has always specified U7+U8 which are RAS2, RAS3 before V2 was added, so when I implemented that firmware I specified those RAS lines to match what I thought the original config was

I think the pinout was swapped in the original lvd qsf, because as @SukkoPera says the firmware works on the A600 version with only 2 chips connected to RAS2/3 and I'm sure I've seen these boards in the 4MB configuration in the past with chips loaded in U7/8 only.

Re: timing warnings I think I just ignored those altogether

To build a 4MB version of the V2 firmware you simply need to uncomment this line in the verilog

OpenAmiga500FastRamExpansion/firmware/V2/Source/SukkoGottaGoFast.v

Line 23 in ef0caab

//`define Size_4MB // 4MB Maximum, Only uses memory chips U7 & U8

You can disable autoconfig in the V2 version by commenting out this line

OpenAmiga500FastRamExpansion/firmware/V2/Source/SukkoGottaGoFast.v

Line 21 in ef0caab

`define autoconfig // If disabled RAM is always mapped to $200000-9FFFFF

When this is done it will map always to $200000-9FFFFF

What I would do is changing line 260 of the verilog code:

OpenAmiga500FastRamExpansion/firmware/V1/source/a600_8mb.v

Lines 259 to 265 in ef0caab

	if( cpu_nreset==0 ) // reset - begin autoconf
	autoconf_on <= 1;
	else
	begin
	if( high_addr==8'hE8 && low_addr[5:2]==4'b1001 ) // $E80048..$E8004E
	autoconf_on <= 0;
	end

and have autoconf_on <= 0; instead of autoconf_on <= 1;. Would that make sense?

From what I can see this would work for the V1 code yes

I notice I didn't set any slew rate settings on my firmware, but if you want to build a V1 firmware perhaps you can copy the slew rate assignments from the A600 8MB 2008 project's QSF file

[avelor-76]

Thanks for all answers and comments! I think I have a proper Quartus configuration then for V1.
I still can’t have my A500 expansion card working (green screen) but I start to believe there’s some hardware or soldering problem that I have to solve first. This can take a few weeks, as I have limited time these days, but I’ll let you now ASAP.

[avelor-76]

Hi, I still could not test the V1 binaries (I only have epm7064 devices here), however I could see that they are exactly the same binaries found in the a600_8mb_addon.zip from the original project by lvd.
The author specifies to use the chips on the right side of his board for the 4Mb variant. Looking at his PCB project, the right side chips correspond indeed to RAS2/3 signals. So he must have used a different pin mapping when compiling, or changed the source code compared to the one included in the project (that uses RAS0/1 for 4Mb instead).

That being said, I still can’t get my board work on my A500 with a self-compiled V1 firmware (can’t use V2 because of kickstart 1.3).
I have a green screen at startup. I tried to disable autoconfig and remove the RAM chips physically, but the only way to have it boot is removing the epm7064 from its socket.