Add support for QuickLogic devices#89

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rw1nkler wants to merge 76 commits into

SymbiFlow:masterfrom

antmicro:ql_upstreaming

Commits on Oct 12, 2020

Initial synth_quicklogic implementation

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rw1nkler
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added ram, fifo and multiplier macros

rakeshm75
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rw1nkler
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Adding -family option in synth_quicklogic option

lalit-quicklogic
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rw1nkler
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Updating cells map & sim files for pp3

lalit-quicklogic
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rw1nkler
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Updating ap3 device support in yosys

lalit-quicklogic
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rw1nkler
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Adding RAM/DSP as blackbox

lalit-quicklogic
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rw1nkler
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LUT optimizations

kgugala
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rw1nkler
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Updating LUT1,2,3 cell mapping to LUT4

lalit-quicklogic
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rw1nkler
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Adding io_reg related primitives

lalit-quicklogic
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rw1nkler
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Update ap3_cells_sim.v

kkumar23
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rw1nkler
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Adding adder support in ap3

lalit-quicklogic
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rw1nkler
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Added techmaps for DFFE, split LUT and FF techmaps into separate files.

mkurc-ant
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rw1nkler
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Updated the synth_quicklogic pass.

mkurc-ant
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rw1nkler
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Adder support in AP3

lalit-quicklogic
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rw1nkler
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Adder implementation where adder is inferred as carry+LUT4 instead of one cell as add

lalit-quicklogic
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rw1nkler
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Separating LUT4 definition for PP3 & AP3

lalit-quicklogic
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rw1nkler
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Merging changes from parent repo

lalit-quicklogic
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rw1nkler
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Fixed synth_quicklogic flow to allow AP3 adder inference

mkurc-ant
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rw1nkler
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Correcting indentation

lalit-quicklogic
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rw1nkler
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Updating latch definition in cells_map file for AP3

lalit-quicklogic
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rw1nkler
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Inferring adder as a cell - full_adder

lalit-quicklogic
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rw1nkler
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Modify options to optimize lut utilization

lalit-quicklogic
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rw1nkler
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Comment freduce

lalit-quicklogic
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rw1nkler
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Adding nlutmap option

lalit-quicklogic
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rw1nkler
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Adding lut optimization support for AP3

lalit-quicklogic
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rw1nkler
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Removing commented code

lalit-quicklogic
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rw1nkler
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Removing ap3_ff_map.v file and updating ap3_ffs_map.v file

lalit-quicklogic
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rw1nkler
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Adding AP2 device support

lalit-quicklogic
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rw1nkler
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Optimizing adder inference for AP3

lalit-quicklogic
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rw1nkler
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Optimizing AP2 utilization

lalit-quicklogic
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rw1nkler
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added support for infering and initialization of bram

tpagarani
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rw1nkler
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abc lut option updated for ap2

lalit-quicklogic
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rw1nkler
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ram init changes

tpagarani
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rw1nkler
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add missing script

tpagarani
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rw1nkler
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Changing lut option in abc for ap2

lalit-quicklogic
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rw1nkler
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update lut option in abc command

lalit-quicklogic
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rw1nkler
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Adding EQN property to LUT instance in edf

lalit-quicklogic
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rw1nkler
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Adding optimizations to PP3 synthesis

lalit-quicklogic
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rw1nkler
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Incorporating code review comments from Karol

lalit-quicklogic
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rw1nkler
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Removing latch definition which is now defined in a separate file

lalit-quicklogic
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rw1nkler
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Reverting lut option as suggested by Maciej

lalit-quicklogic
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rw1nkler
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ram init updates

tpagarani
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rw1nkler
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Modified the ram models to support initialization

rakeshm75
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rw1nkler
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Reenabled LUT4 inference

mkurc-ant
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rw1nkler
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correct the clock ports for RAM8k

tpagarani
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rw1nkler
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modified to correct the yosys compilation error

rakeshm75
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rw1nkler
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Updating copyright name

lalit-quicklogic
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rw1nkler
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initialize bram primitives from hex file

tpagarani
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rw1nkler
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update make file to remove FIFO and RAM block depedencies

tpagarani
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rw1nkler
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change file parameters name

tpagarani
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rw1nkler
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support RAM initialization

rakeshm75
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rw1nkler
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map_bram is run only for PP3 as of now

lalit-quicklogic
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rw1nkler
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Modified pp3_cells_sim.v file to support RAM init

rakeshm75
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rw1nkler
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Adding cell mapping for _DFFSR_NPP_ & _DFFSR_PPP_

lalit-quicklogic
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rw1nkler
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change init file format for 16k block

tpagarani
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rw1nkler
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adding d_buf inference

lalit-quicklogic
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Adding review comments

lalit-quicklogic
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rw1nkler
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Supporting d_buff inference for AP3

lalit-quicklogic
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rw1nkler
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Adding io_map file for AP3

lalit-quicklogic
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rw1nkler
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Infer clk port in in_reg or out_reg as ck_buff for AP3 & AP2 devices.

lalit-quicklogic
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rw1nkler
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Adding external pad property to rst port

lalit-quicklogic
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rw1nkler
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Rectifying clkbuf property on in_reg in AP2

lalit-quicklogic
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rw1nkler
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Fixing an issue in RAM/DSP cell mapping

lalit-quicklogic
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rw1nkler
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Updating in_reg/out_reg def in AP3. Replacing in_reg, out_reg with io_reg in AP2

lalit-quicklogic
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rw1nkler
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Rectifying d_buff declaration issue

lalit-quicklogic
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rw1nkler
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Fixing a compilation error in verilog

lalit-quicklogic
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rw1nkler
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Changing QL_CARRY to full_adder for AP2 & AP3 device

lalit-quicklogic
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Commenting redundant code

lalit-quicklogic
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Replacing adder instance to full_adder for AP2, like AP3

lalit-quicklogic
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Changing to uppercase for primitive cell names of AP3

lalit-quicklogic
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rw1nkler
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Fix wrong rebase strategy remains
rw1nkler
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Substitute YS_OVERRIDE with override
rw1nkler
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Updating IO names to lower case

lalit-quicklogic
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rw1nkler
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Added additional ABC optimizations to synth_quicklogic

mkurc-ant
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rw1nkler
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Allow less efficient use of BRAM resources

olofk
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rw1nkler
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Fix missing new lines and improve code formatting
rw1nkler
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